Has anybody tried marginal read mode of Flash?
What devices have it?
Seems to be a very good feature to maintain the integrity of Flash. Start a New Thread

The bad news is, after I asked TI, they now updated slaz033.pdf to
slaz033a.pdf. They now say that F241x and F261x have FLASH25 bug too
and there is no workaround.

The good news is, I found a workaround. See
http://www.msp430.ubi.pt/forum/viewtopic.php?tr65

--- In m..., "old_cow_yellow"
wrote:
>
> --- In m..., "old_cow_yellow"
> wrote:
> >
> > Has anybody tried marginal read mode of Flash?
> > What devices have it?
> > Seems to be a very good feature to maintain the integrity of Flash.
> > Quoted from slau144d.pdf Section 7.3.6
> ============================================================> Marginal Read Mode
>
> The marginal read mode can be used to verify the integrity of the
> flashmemory contents. This feature is implemented in selected 2xx
> devices; see the device-specific data sheet for availability. During
> marginal read mode marginally programmed flash memory bit locations
> can be detected. Events that could produce this situation include
> improper fFTG settings, or violation of minimum VCC during
> erase/program operations. One method for identifying such memory
> locations would be to periodically perform a checksum calculation over
> a section of flash memory (for example, a flash segment) and repeating
> this procedure with the marginal read mode enabled. If they do not
> match, it could indicate an insufficiently programmed flash memory
> location. It is possible to refresh the affected Flash memory segment
> by disabling marginal read mode, copying to RAM, erasing the flash
> segment, and writing back to it from RAM.
>
> The program checking the flash memory contents must be executed from
> RAM. Executing code from flash will automatically disable the marginal
> read mode. The marginal read modes are controlled by the MRG0 and MRG1
> register bits. Setting MRG1 is used to detect insufficiently
> programmed flash cells containing a "1" (erased bits). Setting MRG0 is
> used to detect insufficiently programmed flash cells containing a "0"
> (programmed bits). Only one of these bits should be set at a time.
> Therefore, a full marginal read check will require two passes of
> checking the flash memory content's integrity. During marginal read
> mode, the flash access speed (MCLK) must be limited to 1MHz (see the
> device-specific data sheet).
>
> ============================================================> Well, I tried it with F2618 silicon rev E. But I could not make it
> work. It seems to have the bug FLASH25 described in slaz039.pdf (for
> F23x/F24x(1)/F2410 silicon rev B). But slaz033.pdf (for F261x/F241x
> silicon rev E) does not indicate bug FLASH24.
> ============================================================> FLASH25 FLASH25 - Bug description
>
> Module: Flash, Function: Marginal Read Mode is not functional
>
> The control bits for marginal read mode contained in the FCTL4
> register are automatically cleared by any flash access. This prevents
> the marginal read mode from being used.
>
> =============================================================> Has anybody else tried?
> Start a New Thread