I'm using an 'F2370 USCI A0 UART and it works fine most of the
time, but it regularly stops receiving bytes. If I reset the
UART and then un-reset it, it will start to receive again.

I'm polling for this condition:

(IFG2 & UCA0RXIFG) || (UCA0STAT & (UCFE|UCOE|UCPE|UCBRK|UCRXERR))

And it will it work for 10-20 messages (each message is about
20 bytes long), and then in the middle of a message, it just
"stops" reporting received bytes/errors: The above expression
never evaluates to true, even though there are still receive
data on the UART's RX pin. I've currently got a 10-byte-time
timeout which allows me to recover by resetting the UART when
the data "stops" in the middle of a message, but that's not
really acceptable.

Here's how I'm intializing the UART:

UCA0CTL1 |= UCSWRST;

UCA0CTL0 = UCPEN +
// UCPAR +
// UCMSB +
// UC7BIT +
// UCSPB +
UCMODE0 +
// UCSYNC +
0;

UCA0CTL1 = UCSSEL_1 + // ACLK
UCRXEIE +
UCBRKIE +
// UCDORM +
// UCTXADDR +
// UCTXBRK +
UCSWRST +
0;

UCA0BR1 = 0;
UCA0BR0 = 27;
UCA0MCTL = UCBRF_0 +
UCBRS_2 +
// UCOS16 +
0;

UCA0CTL1 &= ~UCSWRST;

The receive data stream is from a custom modem demodulator that
I'm debugging, so it's quite possible that the receive data
stream has edges in the "wrong" places, but that shouldn't
cause the UART to lock up completely like it's doing.

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On 2007-12-14, Grant Edwards wrote:
> On 2007-12-14, Grant Edwards wrote:
>>
>> Here's how I'm intializing the UART:
>>
>> UCA0CTL1 |= UCSWRST;
>>
>> UCA0CTL0 = UCPEN +
>> // UCPAR +
>> // UCMSB +
>> // UC7BIT +
>> // UCSPB +
>> UCMODE0 +
>> // UCSYNC +
>> 0;
>
> Oops, that should have been UCMODE_0 not UCMODE0.
> Unfortunately, that doesn't seem to fix the receive lock-up
> problem.

My testing indicates that anytime a rx break is detected, the
UART locks up and won't receive any more characters until it's
been reset.

The last status read before a lock-up is always 0x09
(UCBRK+UCBUSY), and I never see UCBRK except in the last status
read before the UART stops receiving. Once it stops receiving
I can send it data forever and I'll never see another byte.

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On 2007-12-14, Grant Edwards wrote:
>> My testing indicates that anytime a rx break is detected, the
>> UART locks up and won't receive any more characters until it's
>> been reset.
>
> That's the problem: anytime an rx break is detected, the UART
> stops receiving bytes until it's reset/unreset. That sure
> would be a handy thing to mention in the User's Manual.

Doh! I just re-read the errata for the 23x0 family for the Nth
time, and I finally realized that the bug I'm seeing is what's
being described in USCI16.

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On 2007-12-14, Grant Edwards wrote:
>
> Here's how I'm intializing the UART:
>
> UCA0CTL1 |= UCSWRST;
>
> UCA0CTL0 = UCPEN +
> // UCPAR +
> // UCMSB +
> // UC7BIT +
> // UCSPB +
> UCMODE0 +
> // UCSYNC +
> 0;

Oops, that should have been UCMODE_0 not UCMODE0.
Unfortunately, that doesn't seem to fix the receive lock-up
problem.

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> My testing indicates that anytime a rx break is detected, the
> UART locks up and won't receive any more characters until it's
> been reset.

That's the problem: anytime an rx break is detected, the UART
stops receiving bytes until it's reset/unreset. That sure
would be a handy thing to mention in the User's Manual.

I added code to reset the UART anytime a break has been
detected:

lastStatus = UCA0STAT;
b = UCA0RXBUF;
if (lastStatus & UCBRK)
{
// bug in TI hardware: break shuts down UART, so restart it
UCA0CTL1 |= UCSWRST;
UCA0CTL1 &= ~UCSWRST;
}
handleRxByte(b);

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