tintronic wrote:
>
> I think your problem may be much more basic.
> You are using the same USART hardware for both UART and I2C
> interfaces. As far as I know, only one of those can be used at any
> time. I don't know if you have realized this and if you are taking the
> necessary precautions (both hardware and software) when changing
> between modes, but it doesn't seam you are.
> For example, you activate an Rx interrupt for UART, but your I2C init
> activates an TX interrupt, without deactivating the RX interrupt set
> by the UART init.
> I couldn't find you interrupt routines on this thread.
>
> Best Regards,
> Michael K.
>

Interesting, so i was under the impression that the microcontroller i chose
could operate uart and i2c at the same time. On the specs, it shows the
Interface as: USCI (UART/LIN/IrDA/SPI and I2C/SPI) , where as other chips
say USCI (UART/LIN/IrDA/SPI or I2C/SPI). If this is not the case, then I'm
in big trouble. Start a New Thread

Sorry, I was wrong. Your device has two USCI (A&B), where the ones I
use have one or two USART (0&1). I thought you were using the same
USART0 for both interfaces, but you are using USCIA and USCIB, so
there is no problem there.

It would be helpful if you sent your interrupt service routines and
the relevant functions that are called by them.

Best Regards,
Michael K. Start a New Thread

I have grabbed my interrupts and initialization functions for both i2c and
serial. I have also uploaded them as a file in case they arent formatted
correctly in this thread...

Start a New Thread

I am having a similar issue on a F2618 device,
I am using UCB0 in i2c mode and USCIA0 in uart mode.
To try and to understand whats happening I disabled
UCA0TXIE = 0
When the USCIAB0TX_VECTOR is exucuted I see that UCA0TXIFG=1
even though UCA0TXIE = 0
The trouble is that I can't seem to clear UCA0TXIFG
and the interrupt routine wants to process the USCA0 code for the
uart even though the uart interrupt is disabled and the interrupt
is actually for UCB0RX...
What can I do ? are there any comprehensive examples of how to use
shared interrupts on USCI modules ? Start a New Thread

TXIFG is set whenever TXBUF is ready. It is cleared if you load TXBUF
with data (or junk). But when the TX shift-register is empty, it will
automatically copy that data (or junk) form TXBUF, and TXBUF will be
ready again. Thus TXIFG will be set again.

Thus if you have more data to send, just load it to TXBUF and TXIFG
will be cleared. If you do not have more data, you can let TXIFG stay set.

This scheme is designed to keep a steady stream of TX even when the
software that feeds TXBUF has a hiccups. It works fine within the
stream. But you need some extra work to stop the current stream and to
start another stream. Start a New Thread