No, I meant the LPM3 bits in the saved copy (on the stack) of the 
status register. Also, I assume that you do have interrupts enabled 
when you go into LPM3?

Michel

--- In msp430@msp4..., "Johan Schuld" <johan@a...> wrote:
> Hi,
> 
> You mean the NMIIFG bit in IFG1? This is cleared inside the ISR. 
But the ISR
> doest execute at all when in LPM3. When in Active
mode the ISR 
functions as
> it should.
> 
> I test this by setting a (HW) breakpoint inside the ISR of the NMI
> interrupt. The breakpoint isnt reached when in LPM3. As soon as I 
leave LPM3
> to active mode, the breakpiont is reached.
> 
> Also, when in active mode, and the interrupt falls, the breakpoint 
is
> reached immideately.
> 
> Thanks for your help,
> 
> Johan Schuld
> Adesys B.V.
> Postbus 60
> 2290 NR  Wateringen
> 
> Molenweer 4
> 2291 NR  Wateringen
> 
> The Netherlands
> tel: 0174-296389
> fax: 0174-293807
> www.adesys.nl
> 
> > -----Oorspronkelijk bericht-----
> > Van: michelqv [mailto:michel@q...]
> > Verzonden: vrijdag 5 september 2003 19:33
> > Aan: msp430@msp4...
> > Onderwerp: [msp430] Re: NMI when in LPM3
> >
> >
> > Do you modify the stored status register value when executing the 
ISR?
> >
> > Michel
> >
> > --- In msp430@msp4..., "Johan Schuld" <johan@a...>
wrote:
> > > Hello,
> > >
> > > I'm using a MSP430F135 in LPM3. I am using the RST/NMI pin
as 
NMI.
> > The
> > > interrupt handling works as it should when in wakeup mode.
> > >
> > > As soon as I enter LMP3, and I generate the interrupt the 
processor
> > does not
> > > handle it. When I wakeup the processor by some other reason, 
the NMI
> > > interrupt flag is set, and the processor
handles it at that 
time.
> > (the NMI
> > > interrupt situation does not exist anymore on at that time).
> > >
> > > So it seems that the NMI interrupt flag is set when in LPM3, 
but not
> > > handled.
> > >
> > > The manuals say that when in LPM3 any device that is able to
> > generate an
> > > inerrupt (external interrupts and blocks running on ACLK), and 
is
> > serviced.
> > >
> > > I use Timer-A and 2 external interrupt (I/O) pins, and they 
work as
> > it
> > > should in LMP3
> > >
> > > Is NMI an exception ?
> > >
> > > Oh. I use the Quadravox compiler.
> > >
> > > Thanks for your help,
> > >
> > > Johan Schuld
> > > Adesys B.V.
> > > Postbus 60
> > > 2290 NR  Wateringen
> > >
> > > Molenweer 4
> > > 2291 NR  Wateringen
> > >
> > > The Netherlands
> > > tel: 0174-296389
> > > fax: 0174-293807
> > > www.adesys.nl
> >
> >
> >
> > .
> >
> >
> >
> > ">http://docs.yahoo.com/info/terms/
> >
> >
> >

Hi,

Yes, I change this regeister and interrupts are enabled. But note that the
processor doest even serve the ISR.

However, NMI isnt affecteded by the GIE interrupt flag.

Both NMIE and NMIES are setup.

Also, the NMI is working as long as the processor is in Active mode, so it
seems it has something to do with the low power modes.


Johan Schuld
Adesys B.V.
Postbus 60
2290 NR  Wateringen

Molenweer 4
2291 NR  Wateringen

The Netherlands
tel: 0174-296389
fax: 0174-293807
www.adesys.nl

> -----Oorspronkelijk bericht-----
> Van: michelqv [mailto:michel@mich...]
> Verzonden: maandag 8 september 2003 16:08
> Aan: msp430@msp4...
> Onderwerp: [msp430] Re: NMI when in LPM3
>
>
> No, I meant the LPM3 bits in the saved copy (on the stack) of the
> status register. Also, I assume that you do have interrupts enabled
> when you go into LPM3?
>
> Michel
>
> --- In msp430@msp4..., "Johan Schuld" <johan@a...> wrote:
> > Hi,
> >
> > You mean the NMIIFG bit in IFG1? This is cleared inside the ISR.
> But the ISR
> > doest execute at all when in LPM3. When in Active mode the ISR
> functions as
> > it should.
> >
> > I test this by setting a (HW) breakpoint inside the ISR of the NMI
> > interrupt. The breakpoint isnt reached when in LPM3. As soon as I
> leave LPM3
> > to active mode, the breakpiont is reached.
> >
> > Also, when in active mode, and the interrupt falls, the breakpoint
> is
> > reached immideately.
> >
> > Thanks for your help,
> >
> > Johan Schuld
> > Adesys B.V.
> > Postbus 60
> > 2290 NR  Wateringen
> >
> > Molenweer 4
> > 2291 NR  Wateringen
> >
> > The Netherlands
> > tel: 0174-296389
> > fax: 0174-293807
> > www.adesys.nl
> >
> > > -----Oorspronkelijk bericht-----
> > > Van: michelqv [mailto:michel@q...]
> > > Verzonden: vrijdag 5 september 2003 19:33
> > > Aan: msp430@msp4...
> > > Onderwerp: [msp430] Re: NMI when in LPM3
> > >
> > >
> > > Do you modify the stored status register value when executing the
> ISR?
> > >
> > > Michel
> > >
> > > --- In msp430@msp4..., "Johan Schuld"
<johan@a...> wrote:
> > > > Hello,
> > > >
> > > > I'm using a MSP430F135 in LPM3. I am using the RST/NMI
pin as
> NMI.
> > > The
> > > > interrupt handling works as it should when in wakeup mode.
> > > >
> > > > As soon as I enter LMP3, and I generate the interrupt the
> processor
> > > does not
> > > > handle it. When I wakeup the processor by some other reason,
> the NMI
> > > > interrupt flag is set, and the processor handles it at that
> time.
> > > (the NMI
> > > > interrupt situation does not exist anymore on at that time).
> > > >
> > > > So it seems that the NMI interrupt flag is set when in LPM3,
> but not
> > > > handled.
> > > >
> > > > The manuals say that when in LPM3 any device that is able to
> > > generate an
> > > > inerrupt (external interrupts and blocks running on ACLK),
and
> is
> > > serviced.
> > > >
> > > > I use Timer-A and 2 external interrupt (I/O) pins, and they
> work as
> > > it
> > > > should in LMP3
> > > >
> > > > Is NMI an exception ?
> > > >
> > > > Oh. I use the Quadravox compiler.
> > > >
> > > > Thanks for your help,
> > > >
> > > > Johan Schuld
> > > > Adesys B.V.
> > > > Postbus 60
> > > > 2290 NR  Wateringen
> > > >
> > > > Molenweer 4
> > > > 2291 NR  Wateringen
> > > >
> > > > The Netherlands
> > > > tel: 0174-296389
> > > > fax: 0174-293807
> > > > www.adesys.nl
> > >
> > >
> > >
> > > .
> > >
> > >
> > >
> > > ">http://docs.yahoo.com/info/terms/
> > >
> > >
> > >
>
>
>
> .
>
>
>
> ">http://docs.yahoo.com/info/terms/
>
>
>