Hi group-

My MSP430F449 application requires approx 500KHz MCLK.  I'm using a 
32768Hz crystal at XIN and XOUT with external 18pF caps.  By 
incrementally decreasing SCFQCTL, I'm able to lower MCLK.  Refer to 
the following code snippet I use (IAR compiler):

SCFQCTL = SCFQ_1M;
SCFI0 = FLLD_1;
SCFI1 = 0;

FLL_CTL0 = DCOPLUS;
FLL_CTL1 = XT2OFF | SELM_DCO | FLL_DIV_1;

If I change SCFQCTL to SCFQ_512K, OFIFG gets stuck and never clears.  
In fact, the lowest value for SCFQCTL I can go that will work is 
decimal 19 (DCOCLK = (19 + 1) * 32768 or 655360 Hz).  Any lower and 
OFIFG gets stuck.

I'm baffled why I can't go any lower.  I admit I don't completely

understand the FLL clock system.  Can anyone offer any ideas why I 
can't go lower and what I can do to achieve MCLK about 500KHz?

Thanks, John S.

John Speth wrote:

> Hi group-
> 
> My MSP430F449 application requires approx 500KHz MCLK.  I'm using a 
> 32768Hz crystal at XIN and XOUT with external 18pF caps.

Throw the caps away, unless you have a weird crystal. This port is set 
up for watch crystals and has the load caps internally.

   By
> incrementally decreasing SCFQCTL, I'm able to
lower MCLK.  Refer to 
> the following code snippet I use (IAR compiler):
> 
> SCFQCTL = SCFQ_1M;
> SCFI0 = FLLD_1;
> SCFI1 = 0;
> 
> FLL_CTL0 = DCOPLUS;
> FLL_CTL1 = XT2OFF | SELM_DCO | FLL_DIV_1;
> 
> If I change SCFQCTL to SCFQ_512K, OFIFG gets stuck and never clears.  
> In fact, the lowest value for SCFQCTL I can go that will work is 
> decimal 19 (DCOCLK = (19 + 1) * 32768 or 655360 Hz).  Any lower and 
> OFIFG gets stuck.

Typical lowest frequency for the DCO is given in SLAS344B Page 38 as 
typically 0.65MHz. I hope I got this one right Antonio ;@}

Al

> 
> I'm baffled why I can't go any lower.  I admit I don't
completely 
> understand the FLL clock system.  Can anyone offer any ideas why I 
> can't go lower and what I can do to achieve MCLK about 500KHz?
> 
> Thanks, John S.
> 
> 
> 
> 
> .
> 
>  
> 
> ">http://docs.yahoo.com/info/terms/ 
> 
> 
> 

At 00:49 01-10-03 +0930, "onestone":
>Typical lowest frequency for the DCO is given in
SLAS344B Page 38 as
>typically 0.65MHz. I hope I got this one right Antonio ;@}

I agree, I have not experienced with low frequency DCO settings, but the 
fact that it cannot go lower than a certain frequency does make sense.
Actually I found the information on the data sheet a bit confusing and 
cannot say if this does impose a lower limit on the minimum frequency at 
0.65 MHz (typical).
The idea should be that this is the central frquency at which the DCO is 
free running, the FLL can adjust it in a certain range.
Actually let me review a bit the whole thing.  I have time ago succeed to 
set it ( but it was at 6.5 Mhz DCO locked from the 32768 xtal ) and I do 
not remeber the exact sequence of reasoning.
However the main question may be: what is the reason to call for such low 
frequency from the FLL DCO ?  I mean "John Speth" wants 500KHz MCLK, 
but 
most of the time one does not really need to have a slow CPU cycle, while 
the peripherals can be clocked at a fraction of the MCLK clock, if 
necessary for any reason.
This I say because the "slow" FLL- DCO frequency, if ever possible to 
obtain, may be not really stable, an FLL is an FLL ...
Regards
  antonio

> However the main question may be: what is the reason to call for 
such low 
> frequency from the FLL DCO ?  I mean "John
Speth" wants 500KHz 
MCLK,  but 
> most of the time one does not really need to have
a slow CPU cycle, 
while 
> the peripherals can be clocked at a fraction of
the MCLK clock, if 
> necessary for any reason.

The reason I want 500KHz is that we are using an external 16 bit ADC 
that requires a 500KHz 50% DF clock.  The F449 is providing that 
clock.  At 1MHz or higher, I can program the ADC12CLK to provide 1MHz 
and use a DFF to divide by 2 to get a 50% DF ADC clock.  I'd like to 
use the MCLK pin instead and dump the DFF.  It's a cost issue.

Like you, I find the the data sheet confusing.  It just doesn't tell 
the whole story.  But I'll accept that it won't go lower than 
650KHz.  But I have to wonder why, then, does TI provide the 
capability via register range of SCFQCTL to go that low?  Even IAR 
provides header file contants that would suggest it can go as low as 
65KHz!

JJS

John Speth wrote:


>The reason I want 500KHz is that we are using an
external 16 bit ADC
>that requires a 500KHz 50% DF clock.  The F449 is providing that
>clock.  At 1MHz or higher, I can program the ADC12CLK to provide 1MHz
>and use a DFF to divide by 2 to get a 50% DF ADC clock.  I'd like to
>use the MCLK pin instead and dump the DFF.  It's a cost issue.

There are other possibilities.  Cost is always an issue, of course, but if 
your A/D converter does need exactly 500KHz at 50% duty cycle, the FLL 
provided output may not fit the purpose. Keep in mind that the MCLK derived 
from the FLL DCO is not stable.
Frequency variations of the DCO are stabilized by the FLL, but this is not 
without problems
I take the following from SLAU056B

"
The accumulated error in MCLK/SMCLK tends to zero over a long period. The
10-bit FLL+ integrator is automatically adjusted every period of the ACLK.
Thus, a positive frequency deviation over one ACLK period is compensated
with a negative deviation over the next ACLK period. Variation between
MCLK/SMCLK clock periods can be approximately 10% due to the modulator
mixing of DCO taps, while the accumulated system clock error over longer time
periods is zero."
This means that from one period to the other of the ACLK (32KHz) the MCLK 
can vary 10% up or down, this is a noticeable variation over a small 
(30microsecond) period.
If your A/D converter can accept this, I think it could as well take 650KHz 
and be happy as well.
In other words: maybe you really have to get your 500KHz exactly, but if 
this is the case I would recommend using a 500KHz Xtal on the secondary 
oscillator.
However, I do not think it is easy to find a 500KHz Xtal on the market, and 
it may cost a bit, if you find it.
Also I would not bet on the 50% duty cycle requirement being easily met, as 
well.
So what I would really do, in this situation is use one of the Timer 
outputs TA or TB, supply them with an even division of a reasonable Xtal 
frequency and use this Xtal as the MCLK source as well. With the added 
benefit of a faster cycle time for whatever you want the micro to do.
1, 2, 4, 8 MHz Xtal are common, you can also use a ceramic resonator, which 
is lower price, although less stable.

You can do the same ( I mean use a timer output) deriving it from the 
FLL+DCO frequency of course, but with the problems discussed above, in that 
case you shoul use a multiplying factor that takes you to the desidered 
frequency.
In one of my projects the settings are :

mov.b   #(119),&SCFQCTL
mov.b   #0xF,&SCFI1
mov.b   #(0x40+FN3),&SCFI0
bis.b   #DCOPLUS,&FLL_CTL0

this gives a 240 times 32768 clock = 7864320 Hz
   ( that was to keep things just a bit lower of the certified 8 MHz)

if you go to 244 times you will have 7995392 ie almost 8MHz

it is rather easy to divide this by 16 and get the 500KHz for the A/D, 
using a timer function if available

If your "F449 timer functions are already used up ... too bad, I do not 
know what else to suggest.
As for the FLL going down to 65 KHz, I do suspect that it is possible, but 
the thing is difficult to dig out and I have not experienced it.



>Like you, I find the the data sheet confusing.  It
just doesn't tell
>the whole story.  But I'll accept that it won't go lower than
>650KHz.  But I have to wonder why, then, does TI provide the
>capability via register range of SCFQCTL to go that low?  Even IAR
>provides header file contants that would suggest it can go as low as
>65KHz!
>
>JJS
>
>

Hi Antonio, I too wondered why John anted such a low clock, when you can 
subdivide for all the peripherals. I'm alwasy looking for the other, 
faster clocks! That's why I kep my mouth shut. My bias is well known ;@}

Al

Ing. Morra Antonio wrote:

> At 00:49 01-10-03 +0930, "onestone":
> 
>>Typical lowest frequency for the DCO is given in SLAS344B Page 38 as
>>typically 0.65MHz. I hope I got this one right Antonio ;@}
> 
> 
> I agree, I have not experienced with low frequency DCO settings, but the 
> fact that it cannot go lower than a certain frequency does make sense.
> Actually I found the information on the data sheet a bit confusing and 
> cannot say if this does impose a lower limit on the minimum frequency at 
> 0.65 MHz (typical).
> The idea should be that this is the central frquency at which the DCO is 
> free running, the FLL can adjust it in a certain range.
> Actually let me review a bit the whole thing.  I have time ago succeed to 
> set it ( but it was at 6.5 Mhz DCO locked from the 32768 xtal ) and I do 
> not remeber the exact sequence of reasoning.
> However the main question may be: what is the reason to call for such low 
> frequency from the FLL DCO ?  I mean "John Speth" wants 500KHz
MCLK,  but 
> most of the time one does not really need to have a slow CPU cycle, while 
> the peripherals can be clocked at a fraction of the MCLK clock, if 
> necessary for any reason.
> This I say because the "slow" FLL- DCO frequency, if ever
possible to 
> obtain, may be not really stable, an FLL is an FLL ...
> Regards
>   antonio
> 
> 
> 
> 
> 
> 
> 
> .
> 
>  
> 
> ">http://docs.yahoo.com/info/terms/ 
> 
> 
> 

You have the choice of outputting ADC12CLK, MCLK, SMCLK or ACLK. These 
can radily be divided down to suit your external part. MCLK and SMCLK 
can be derived from a precision external crystal, or the DCO/FLL. Most 
peripherals can select Aclk/mclk or Smclk as there timing source, this 
is one of the very useful features of the MSP430. You can, in most 
circumstances afford to dedicate a clock (typically SMCLK) for just such 
a function as this. As to whether you choose to derive it from the FLL, 
with possible (but I think fairly unlikely) problems with duty cycle and 
possible short term inaccuracy, or from an external source, such as a 
cheap resonator or crystal is up to you. 4Mhz resonators are a few 
cents, crystals a dollar. I'd take the FLL but have an option to fit a 
resonator on the PCB.

Al

John Speth wrote:

>>However the main question may be: what is the
reason to call for 
> 
> such low 
> 
>>frequency from the FLL DCO ?  I mean "John Speth" wants 500KHz

> 
> MCLK,  but 
> 
>>most of the time one does not really need to have a slow CPU cycle, 
> 
> while 
> 
>>the peripherals can be clocked at a fraction of the MCLK clock, if 
>>necessary for any reason.
> 
> 
> The reason I want 500KHz is that we are using an external 16 bit ADC 
> that requires a 500KHz 50% DF clock.  The F449 is providing that 
> clock.  At 1MHz or higher, I can program the ADC12CLK to provide 1MHz 
> and use a DFF to divide by 2 to get a 50% DF ADC clock.  I'd like to 
> use the MCLK pin instead and dump the DFF.  It's a cost issue.
> 
> Like you, I find the the data sheet confusing.  It just doesn't tell 
> the whole story.  But I'll accept that it won't go lower than 
> 650KHz.  But I have to wonder why, then, does TI provide the 
> capability via register range of SCFQCTL to go that low?  Even IAR 
> provides header file contants that would suggest it can go as low as 
> 65KHz!
> 
> JJS
> 
> 
> 
> 
> .
> 
>  
> 
> ">http://docs.yahoo.com/info/terms/ 
> 
> 
>