Wouldn't help, the problem is further up, and a lower body transplant
could be risky, I might end up with boobs or something! Hmmm! thinking
on it would that be So bad?
Al
On 18/02/2015 9:38 AM, Jake Grajewski p...@gmail.com [msp430] wrote:
> or get new hands ^^
>
> On Tue, Feb 17, 2015 at 3:02 PM, Onestone o...@bigpond.net.au
> [msp430]
> > wrote:
>
> Well typing can be difficult when you only have limited use of
> your hands. I'll try to do better next time.
>
> Al
> On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com
> [msp430] wrote:
>> I believe you were looking for “frightening” not
“fightening".
>>
>> From: "msp430@yahoogroups. com"
>> >
>> Reply-To: "msp430@yahoogroups. com"
>>
>> >
>> Date: Tuesday, February 17, 2015 at 3:07 PM
>> To: "msp430@yahoogroups. com"
>> >
>> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>>
>> Why oh why are you bit banging this when the MSP430 has an
>> extremely simple UART in hardware. Are interrupts that fightening?
>>
>> Al
>>
>> On 18/02/2015 2:21 AM, m...@yahoo.com
>> [msp430] wrote:
>>>
>>>
>>>
>>> Hello, I'm trying to communicate with my RF module through UART
>>> interface. However, I get many errors even with low load. I
>>> suspect that I have an issue with the way that I configure the
>>> clock or the UART.
>>>
>>>
>>> Basically, for the UART functionality I use
>>> http://glitovsky.com/blog/?p00
>>>
>>> (I configured the connection as 8N1 at 115200).
>>>
>>>
>>> The clock configuration below is used with MCLK = 25 MHz ( when
>>> I use it with MCLK MHz I cannot communicate with the UART
>>> module at all ) .
>>>
>>>
>>> P5SEL |= 0x0C;
>>>
>>> /* Select REF0 for FLL reference. */
>>>
>>> UCSCTL3 &= ~SELREF_7;
>>>
>>> UCSCTL3 |= SELREF_2;
>>>
>>>
>>> /* Set ACLK to use REF0CLK.
>>>
>>> * Set SMCLK to use the DCO.
>>>
>>> */
>>>
>>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>>
>>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>>
>>> /* Initialize FLL. */
>>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>>
>>> XT2_Start(XT2DRIVE_0);
>>>
>>> UCSCTL4 &= ~SELA_7;
>>> UCSCTL4 |= SELA_2;
>>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>>> /* Enable interrupt for TBCCR0. */
>>> TBCCTL0 = CCIE;
>>> /* Number of ticks per millisecond. */
>>> clock.aclk = 32768;
>>> clock.ticks_per_interrupt = clock.aclk / 1000;
>>> TBCCR0 = clock.ticks_per_interrupt;
>>>
>>> /* Use ACLK, set timer to up-count mode, and start timer at
>>> zero. */
>>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>>
>>> /* Enable interrupts. */
>>> __bis_SR_register(GIE);
>>> Thanks,
>>> Mike
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>> --
> Thomas J. Grajewski
MSP430F5528 - Clock and UART
Started by ●February 17, 2015
Reply by ●February 17, 20152015-02-17
Reply by ●February 17, 20152015-02-17
Guys please, I started getting a lot of your discussion emails from you , how
can I stop this , I mean to Unsubscribe from this msp430 group??????????
On Tuesday, February 17, 2015 3:17 PM, "Onestone o...@bigpond.net.au [msp430]" wrote:
Wouldn't help, the problem is further up, and a lower body transplant could be risky, I might end up with boobs or something! Hmmm! thinking on it would that be So bad?
Al
On 18/02/2015 9:38 AM, Jake Grajewski p...@gmail.com [msp430] wrote:
or get new hands ^^
On Tue, Feb 17, 2015 at 3:02 PM, Onestone o...@bigpond.net.au [msp430] wrote:
Well typing can be difficult when you only have limited use of your hands. I'll try to do better next time.
Al
On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com [msp430] wrote:
I believe you were looking for “frightening” not “fightening".
From: "msp430@yahoogroups. com"
Reply-To: "msp430@yahoogroups. com"
Date: Tuesday, February 17, 2015 at 3:07 PM
To: "msp430@yahoogroups. com"
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Why oh why are you bit banging this when the MSP430 has an extremely simple UART in hardware. Are interrupts that fightening?
Al
On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
Hello, I'm trying to communicate with my RF module through UART interface. However, I get many errors even with low load. I suspect that I have an issue with the way that I configure the clock or the UART.
Basically, for the UART functionality I use http://glitovsky.com/blog/?p00 (I configured the connection as 8N1 at 115200).
The clock configuration below is used with MCLK = 25 MHz ( when I use it with MCLK MHz I cannot communicate with the UART module at all ) .
P5SEL |= 0x0C;
/* Select REF0 for FLL reference. */ UCSCTL3 &= ~SELREF_7; UCSCTL3 |= SELREF_2;
/* Set ACLK to use REF0CLK. * Set SMCLK to use the DCO. */ UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7; UCSCTL4 |= SELA_2 | SELS_4 | SELM_4; /* Initialize FLL. */ Init_FLL_Settle(mclk/1000L, mclk/32768);
XT2_Start(XT2DRIVE_0);
UCSCTL4 &= ~SELA_7;
UCSCTL4 |= SELA_2; UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN; /* Enable interrupt for TBCCR0. */ TBCCTL0 = CCIE; /* Number of ticks per millisecond. */ clock.aclk = 32768; clock.ticks_per_interrupt = clock.aclk / 1000; TBCCR0 = clock.ticks_per_interrupt;
/* Use ACLK, set timer to up-count mode, and start timer at zero. */ TBCTL = TBSSEL_1 | MC_2 | TBCLR;
/* Enable interrupts. */ __bis_SR_register(GIE); Thanks, Mike
--
Thomas J. Grajewski
#yiv0952572577 #yiv0952572577 -- #yiv0952572577ygrp-mkp {border:1px solid #d8d8d8;font-family:Arial;margin:10px 0;padding:0 10px;}#yiv0952572577 #yiv0952572577ygrp-mkp hr {border:1px solid #d8d8d8;}#yiv0952572577 #yiv0952572577ygrp-mkp #yiv0952572577hd {color:#628c2a;font-size:85%;font-weight:700;line-height:122%;margin:10px 0;}#yiv0952572577 #yiv0952572577ygrp-mkp #yiv0952572577ads {margin-bottom:10px;}#yiv0952572577 #yiv0952572577ygrp-mkp .yiv0952572577ad {padding:0 0;}#yiv0952572577 #yiv0952572577ygrp-mkp .yiv0952572577ad p {margin:0;}#yiv0952572577 #yiv0952572577ygrp-mkp .yiv0952572577ad a {color:#0000ff;text-decoration:none;}#yiv0952572577 #yiv0952572577ygrp-sponsor #yiv0952572577ygrp-lc {font-family:Arial;}#yiv0952572577 #yiv0952572577ygrp-sponsor #yiv0952572577ygrp-lc #yiv0952572577hd {margin:10px 0px;font-weight:700;font-size:78%;line-height:122%;}#yiv0952572577 #yiv0952572577ygrp-sponsor #yiv0952572577ygrp-lc .yiv0952572577ad {margin-bottom:10px;padding:0 0;}#yiv0952572577 #yiv0952572577actions {font-family:Verdana;font-size:11px;padding:10px 0;}#yiv0952572577 #yiv0952572577activity {background-color:#e0ecee;float:left;font-family:Verdana;font-size:10px;padding:10px;}#yiv0952572577 #yiv0952572577activity span {font-weight:700;}#yiv0952572577 #yiv0952572577activity span:first-child {text-transform:uppercase;}#yiv0952572577 #yiv0952572577activity span a {color:#5085b6;text-decoration:none;}#yiv0952572577 #yiv0952572577activity span span {color:#ff7900;}#yiv0952572577 #yiv0952572577activity span .yiv0952572577underline {text-decoration:underline;}#yiv0952572577 .yiv0952572577attach {clear:both;display:table;font-family:Arial;font-size:12px;padding:10px 0;width:400px;}#yiv0952572577 .yiv0952572577attach div a {text-decoration:none;}#yiv0952572577 .yiv0952572577attach img {border:none;padding-right:5px;}#yiv0952572577 .yiv0952572577attach label {display:block;margin-bottom:5px;}#yiv0952572577 .yiv0952572577attach label a {text-decoration:none;}#yiv0952572577 blockquote {margin:0 0 0 4px;}#yiv0952572577 .yiv0952572577bold {font-family:Arial;font-size:13px;font-weight:700;}#yiv0952572577 .yiv0952572577bold a {text-decoration:none;}#yiv0952572577 dd.yiv0952572577last p a {font-family:Verdana;font-weight:700;}#yiv0952572577 dd.yiv0952572577last p span {margin-right:10px;font-family:Verdana;font-weight:700;}#yiv0952572577 dd.yiv0952572577last p span.yiv0952572577yshortcuts {margin-right:0;}#yiv0952572577 div.yiv0952572577attach-table div div a {text-decoration:none;}#yiv0952572577 div.yiv0952572577attach-table {width:400px;}#yiv0952572577 div.yiv0952572577file-title a, #yiv0952572577 div.yiv0952572577file-title a:active, #yiv0952572577 div.yiv0952572577file-title a:hover, #yiv0952572577 div.yiv0952572577file-title a:visited {text-decoration:none;}#yiv0952572577 div.yiv0952572577photo-title a, #yiv0952572577 div.yiv0952572577photo-title a:active, #yiv0952572577 div.yiv0952572577photo-title a:hover, #yiv0952572577 div.yiv0952572577photo-title a:visited {text-decoration:none;}#yiv0952572577 div#yiv0952572577ygrp-mlmsg #yiv0952572577ygrp-msg p a span.yiv0952572577yshortcuts {font-family:Verdana;font-size:10px;font-weight:normal;}#yiv0952572577 .yiv0952572577green {color:#628c2a;}#yiv0952572577 .yiv0952572577MsoNormal {margin:0 0 0 0;}#yiv0952572577 o {font-size:0;}#yiv0952572577 #yiv0952572577photos div {float:left;width:72px;}#yiv0952572577 #yiv0952572577photos div div {border:1px solid #666666;height:62px;overflow:hidden;width:62px;}#yiv0952572577 #yiv0952572577photos div label {color:#666666;font-size:10px;overflow:hidden;text-align:center;white-space:nowrap;width:64px;}#yiv0952572577 #yiv0952572577reco-category {font-size:77%;}#yiv0952572577 #yiv0952572577reco-desc {font-size:77%;}#yiv0952572577 .yiv0952572577replbq {margin:4px;}#yiv0952572577 #yiv0952572577ygrp-actbar div a:first-child {margin-right:2px;padding-right:5px;}#yiv0952572577 #yiv0952572577ygrp-mlmsg {font-size:13px;font-family:Arial, helvetica, clean, sans-serif;}#yiv0952572577 #yiv0952572577ygrp-mlmsg table {font-size:inherit;font:100%;}#yiv0952572577 #yiv0952572577ygrp-mlmsg select, #yiv0952572577 input, #yiv0952572577 textarea {font:99% Arial, Helvetica, clean, sans-serif;}#yiv0952572577 #yiv0952572577ygrp-mlmsg pre, #yiv0952572577 code {font:115% monospace;}#yiv0952572577 #yiv0952572577ygrp-mlmsg * {line-height:1.22em;}#yiv0952572577 #yiv0952572577ygrp-mlmsg #yiv0952572577logo {padding-bottom:10px;}#yiv0952572577 #yiv0952572577ygrp-msg p a {font-family:Verdana;}#yiv0952572577 #yiv0952572577ygrp-msg p#yiv0952572577attach-count span {color:#1E66AE;font-weight:700;}#yiv0952572577 #yiv0952572577ygrp-reco #yiv0952572577reco-head {color:#ff7900;font-weight:700;}#yiv0952572577 #yiv0952572577ygrp-reco {margin-bottom:20px;padding:0px;}#yiv0952572577 #yiv0952572577ygrp-sponsor #yiv0952572577ov li a {font-size:130%;text-decoration:none;}#yiv0952572577 #yiv0952572577ygrp-sponsor #yiv0952572577ov li {font-size:77%;list-style-type:square;padding:6px 0;}#yiv0952572577 #yiv0952572577ygrp-sponsor #yiv0952572577ov ul {margin:0;padding:0 0 0 8px;}#yiv0952572577 #yiv0952572577ygrp-text {font-family:Georgia;}#yiv0952572577 #yiv0952572577ygrp-text p {margin:0 0 1em 0;}#yiv0952572577 #yiv0952572577ygrp-text tt {font-size:120%;}#yiv0952572577 #yiv0952572577ygrp-vital ul li:last-child {border-right:none !important;}#yiv0952572577
On Tuesday, February 17, 2015 3:17 PM, "Onestone o...@bigpond.net.au [msp430]" wrote:
Wouldn't help, the problem is further up, and a lower body transplant could be risky, I might end up with boobs or something! Hmmm! thinking on it would that be So bad?
Al
On 18/02/2015 9:38 AM, Jake Grajewski p...@gmail.com [msp430] wrote:
or get new hands ^^
On Tue, Feb 17, 2015 at 3:02 PM, Onestone o...@bigpond.net.au [msp430] wrote:
Well typing can be difficult when you only have limited use of your hands. I'll try to do better next time.
Al
On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com [msp430] wrote:
I believe you were looking for “frightening” not “fightening".
From: "msp430@yahoogroups. com"
Reply-To: "msp430@yahoogroups. com"
Date: Tuesday, February 17, 2015 at 3:07 PM
To: "msp430@yahoogroups. com"
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Why oh why are you bit banging this when the MSP430 has an extremely simple UART in hardware. Are interrupts that fightening?
Al
On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
Hello, I'm trying to communicate with my RF module through UART interface. However, I get many errors even with low load. I suspect that I have an issue with the way that I configure the clock or the UART.
Basically, for the UART functionality I use http://glitovsky.com/blog/?p00 (I configured the connection as 8N1 at 115200).
The clock configuration below is used with MCLK = 25 MHz ( when I use it with MCLK MHz I cannot communicate with the UART module at all ) .
P5SEL |= 0x0C;
/* Select REF0 for FLL reference. */ UCSCTL3 &= ~SELREF_7; UCSCTL3 |= SELREF_2;
/* Set ACLK to use REF0CLK. * Set SMCLK to use the DCO. */ UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7; UCSCTL4 |= SELA_2 | SELS_4 | SELM_4; /* Initialize FLL. */ Init_FLL_Settle(mclk/1000L, mclk/32768);
XT2_Start(XT2DRIVE_0);
UCSCTL4 &= ~SELA_7;
UCSCTL4 |= SELA_2; UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN; /* Enable interrupt for TBCCR0. */ TBCCTL0 = CCIE; /* Number of ticks per millisecond. */ clock.aclk = 32768; clock.ticks_per_interrupt = clock.aclk / 1000; TBCCR0 = clock.ticks_per_interrupt;
/* Use ACLK, set timer to up-count mode, and start timer at zero. */ TBCTL = TBSSEL_1 | MC_2 | TBCLR;
/* Enable interrupts. */ __bis_SR_register(GIE); Thanks, Mike
--
Thomas J. Grajewski
#yiv0952572577 #yiv0952572577 -- #yiv0952572577ygrp-mkp {border:1px solid #d8d8d8;font-family:Arial;margin:10px 0;padding:0 10px;}#yiv0952572577 #yiv0952572577ygrp-mkp hr {border:1px solid #d8d8d8;}#yiv0952572577 #yiv0952572577ygrp-mkp #yiv0952572577hd {color:#628c2a;font-size:85%;font-weight:700;line-height:122%;margin:10px 0;}#yiv0952572577 #yiv0952572577ygrp-mkp #yiv0952572577ads {margin-bottom:10px;}#yiv0952572577 #yiv0952572577ygrp-mkp .yiv0952572577ad {padding:0 0;}#yiv0952572577 #yiv0952572577ygrp-mkp .yiv0952572577ad p {margin:0;}#yiv0952572577 #yiv0952572577ygrp-mkp .yiv0952572577ad a {color:#0000ff;text-decoration:none;}#yiv0952572577 #yiv0952572577ygrp-sponsor #yiv0952572577ygrp-lc {font-family:Arial;}#yiv0952572577 #yiv0952572577ygrp-sponsor #yiv0952572577ygrp-lc #yiv0952572577hd {margin:10px 0px;font-weight:700;font-size:78%;line-height:122%;}#yiv0952572577 #yiv0952572577ygrp-sponsor #yiv0952572577ygrp-lc .yiv0952572577ad {margin-bottom:10px;padding:0 0;}#yiv0952572577 #yiv0952572577actions {font-family:Verdana;font-size:11px;padding:10px 0;}#yiv0952572577 #yiv0952572577activity {background-color:#e0ecee;float:left;font-family:Verdana;font-size:10px;padding:10px;}#yiv0952572577 #yiv0952572577activity span {font-weight:700;}#yiv0952572577 #yiv0952572577activity span:first-child {text-transform:uppercase;}#yiv0952572577 #yiv0952572577activity span a {color:#5085b6;text-decoration:none;}#yiv0952572577 #yiv0952572577activity span span {color:#ff7900;}#yiv0952572577 #yiv0952572577activity span .yiv0952572577underline {text-decoration:underline;}#yiv0952572577 .yiv0952572577attach {clear:both;display:table;font-family:Arial;font-size:12px;padding:10px 0;width:400px;}#yiv0952572577 .yiv0952572577attach div a {text-decoration:none;}#yiv0952572577 .yiv0952572577attach img {border:none;padding-right:5px;}#yiv0952572577 .yiv0952572577attach label {display:block;margin-bottom:5px;}#yiv0952572577 .yiv0952572577attach label a {text-decoration:none;}#yiv0952572577 blockquote {margin:0 0 0 4px;}#yiv0952572577 .yiv0952572577bold {font-family:Arial;font-size:13px;font-weight:700;}#yiv0952572577 .yiv0952572577bold a {text-decoration:none;}#yiv0952572577 dd.yiv0952572577last p a {font-family:Verdana;font-weight:700;}#yiv0952572577 dd.yiv0952572577last p span {margin-right:10px;font-family:Verdana;font-weight:700;}#yiv0952572577 dd.yiv0952572577last p span.yiv0952572577yshortcuts {margin-right:0;}#yiv0952572577 div.yiv0952572577attach-table div div a {text-decoration:none;}#yiv0952572577 div.yiv0952572577attach-table {width:400px;}#yiv0952572577 div.yiv0952572577file-title a, #yiv0952572577 div.yiv0952572577file-title a:active, #yiv0952572577 div.yiv0952572577file-title a:hover, #yiv0952572577 div.yiv0952572577file-title a:visited {text-decoration:none;}#yiv0952572577 div.yiv0952572577photo-title a, #yiv0952572577 div.yiv0952572577photo-title a:active, #yiv0952572577 div.yiv0952572577photo-title a:hover, #yiv0952572577 div.yiv0952572577photo-title a:visited {text-decoration:none;}#yiv0952572577 div#yiv0952572577ygrp-mlmsg #yiv0952572577ygrp-msg p a span.yiv0952572577yshortcuts {font-family:Verdana;font-size:10px;font-weight:normal;}#yiv0952572577 .yiv0952572577green {color:#628c2a;}#yiv0952572577 .yiv0952572577MsoNormal {margin:0 0 0 0;}#yiv0952572577 o {font-size:0;}#yiv0952572577 #yiv0952572577photos div {float:left;width:72px;}#yiv0952572577 #yiv0952572577photos div div {border:1px solid #666666;height:62px;overflow:hidden;width:62px;}#yiv0952572577 #yiv0952572577photos div label {color:#666666;font-size:10px;overflow:hidden;text-align:center;white-space:nowrap;width:64px;}#yiv0952572577 #yiv0952572577reco-category {font-size:77%;}#yiv0952572577 #yiv0952572577reco-desc {font-size:77%;}#yiv0952572577 .yiv0952572577replbq {margin:4px;}#yiv0952572577 #yiv0952572577ygrp-actbar div a:first-child {margin-right:2px;padding-right:5px;}#yiv0952572577 #yiv0952572577ygrp-mlmsg {font-size:13px;font-family:Arial, helvetica, clean, sans-serif;}#yiv0952572577 #yiv0952572577ygrp-mlmsg table {font-size:inherit;font:100%;}#yiv0952572577 #yiv0952572577ygrp-mlmsg select, #yiv0952572577 input, #yiv0952572577 textarea {font:99% Arial, Helvetica, clean, sans-serif;}#yiv0952572577 #yiv0952572577ygrp-mlmsg pre, #yiv0952572577 code {font:115% monospace;}#yiv0952572577 #yiv0952572577ygrp-mlmsg * {line-height:1.22em;}#yiv0952572577 #yiv0952572577ygrp-mlmsg #yiv0952572577logo {padding-bottom:10px;}#yiv0952572577 #yiv0952572577ygrp-msg p a {font-family:Verdana;}#yiv0952572577 #yiv0952572577ygrp-msg p#yiv0952572577attach-count span {color:#1E66AE;font-weight:700;}#yiv0952572577 #yiv0952572577ygrp-reco #yiv0952572577reco-head {color:#ff7900;font-weight:700;}#yiv0952572577 #yiv0952572577ygrp-reco {margin-bottom:20px;padding:0px;}#yiv0952572577 #yiv0952572577ygrp-sponsor #yiv0952572577ov li a {font-size:130%;text-decoration:none;}#yiv0952572577 #yiv0952572577ygrp-sponsor #yiv0952572577ov li {font-size:77%;list-style-type:square;padding:6px 0;}#yiv0952572577 #yiv0952572577ygrp-sponsor #yiv0952572577ov ul {margin:0;padding:0 0 0 8px;}#yiv0952572577 #yiv0952572577ygrp-text {font-family:Georgia;}#yiv0952572577 #yiv0952572577ygrp-text p {margin:0 0 1em 0;}#yiv0952572577 #yiv0952572577ygrp-text tt {font-size:120%;}#yiv0952572577 #yiv0952572577ygrp-vital ul li:last-child {border-right:none !important;}#yiv0952572577
Reply by ●February 17, 20152015-02-17
Touche, but a good software developer *never *uses untested libraries, now
that would just be silly. ;-P.
[image: Caption this picture]
On Tue, Feb 17, 2015 at 3:15 PM, Onestone o...@bigpond.net.au [msp430] <
m...> wrote:
> Wrong, totally. the first rule of software development is that the best
> code is the one that you personally know has been fully debugged, and
> usually that is one that you wrote. If you trust others to write better
> code than you then you are asking for a world of grief.
>
> Who says I'm a bear? Anyway it's 'built in' not 'build in'. :-P
>
> Al
> On 18/02/2015 9:38 AM, Jake Grajewski p...@gmail.com [msp430] wrote:
>
> Hi All,
>
> First off, The first rule of software development is that the best code
> is the one you didn't have to write ^^.
>
> I agree with Al here, why aren't you using the build in UART tool in the
> microprocessor. It is build to be used in this way, and the only reason
> ever not to is if you have to use a certain chip and you have run out of
> UART ports to use.
>
> @Martin: Now you are just poking the bear aren't you.
>
> Cheers,
> Jake
>
> On Tue, Feb 17, 2015 at 2:07 PM, Onestone o...@bigpond.net.au
> [msp430] wrote:
>
>> Why oh why are you bit banging this when the MSP430 has an extremely
>> simple UART in hardware. Are interrupts that fightening?
>>
>> Al
>> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>> Hello, I'm trying to communicate with my RF module through UART
>> interface. However, I get many errors even with low load. I suspect that
>> I have an issue with the way that I configure the clock or the UART.
>> Basically, for the UART functionality I use
>> http://glitovsky.com/blog/?p00
>>
>> (I configured the connection as 8N1 at 115200).
>> The clock configuration below is used with MCLK = 25 MHz ( when I use
>> it with MCLK MHz I cannot communicate with the UART module at all ) .
>> P5SEL |= 0x0C;
>>
>> /* Select REF0 for FLL reference. */
>>
>> UCSCTL3 &= ~SELREF_7;
>>
>> UCSCTL3 |= SELREF_2;
>> /* Set ACLK to use REF0CLK.
>>
>> * Set SMCLK to use the DCO.
>>
>> */
>>
>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>
>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>> /* Initialize FLL. */
>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>
>> XT2_Start(XT2DRIVE_0);
>>
>> UCSCTL4 &= ~SELA_7;
>> UCSCTL4 |= SELA_2;
>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>> /* Enable interrupt for TBCCR0. */
>> TBCCTL0 = CCIE;
>>
>> /* Number of ticks per millisecond. */
>> clock.aclk = 32768;
>> clock.ticks_per_interrupt = clock.aclk / 1000;
>> TBCCR0 = clock.ticks_per_interrupt;
>>
>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>
>> /* Enable interrupts. */
>> __bis_SR_register(GIE);
>> Thanks,
>> Mike
>>
> --
> Thomas J. Grajewski
>
>
--
Thomas J. Grajewski
that would just be silly. ;-P.
[image: Caption this picture]
On Tue, Feb 17, 2015 at 3:15 PM, Onestone o...@bigpond.net.au [msp430] <
m...> wrote:
> Wrong, totally. the first rule of software development is that the best
> code is the one that you personally know has been fully debugged, and
> usually that is one that you wrote. If you trust others to write better
> code than you then you are asking for a world of grief.
>
> Who says I'm a bear? Anyway it's 'built in' not 'build in'. :-P
>
> Al
> On 18/02/2015 9:38 AM, Jake Grajewski p...@gmail.com [msp430] wrote:
>
> Hi All,
>
> First off, The first rule of software development is that the best code
> is the one you didn't have to write ^^.
>
> I agree with Al here, why aren't you using the build in UART tool in the
> microprocessor. It is build to be used in this way, and the only reason
> ever not to is if you have to use a certain chip and you have run out of
> UART ports to use.
>
> @Martin: Now you are just poking the bear aren't you.
>
> Cheers,
> Jake
>
> On Tue, Feb 17, 2015 at 2:07 PM, Onestone o...@bigpond.net.au
> [msp430] wrote:
>
>> Why oh why are you bit banging this when the MSP430 has an extremely
>> simple UART in hardware. Are interrupts that fightening?
>>
>> Al
>> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>> Hello, I'm trying to communicate with my RF module through UART
>> interface. However, I get many errors even with low load. I suspect that
>> I have an issue with the way that I configure the clock or the UART.
>> Basically, for the UART functionality I use
>> http://glitovsky.com/blog/?p00
>>
>> (I configured the connection as 8N1 at 115200).
>> The clock configuration below is used with MCLK = 25 MHz ( when I use
>> it with MCLK MHz I cannot communicate with the UART module at all ) .
>> P5SEL |= 0x0C;
>>
>> /* Select REF0 for FLL reference. */
>>
>> UCSCTL3 &= ~SELREF_7;
>>
>> UCSCTL3 |= SELREF_2;
>> /* Set ACLK to use REF0CLK.
>>
>> * Set SMCLK to use the DCO.
>>
>> */
>>
>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>
>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>> /* Initialize FLL. */
>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>
>> XT2_Start(XT2DRIVE_0);
>>
>> UCSCTL4 &= ~SELA_7;
>> UCSCTL4 |= SELA_2;
>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>> /* Enable interrupt for TBCCR0. */
>> TBCCTL0 = CCIE;
>>
>> /* Number of ticks per millisecond. */
>> clock.aclk = 32768;
>> clock.ticks_per_interrupt = clock.aclk / 1000;
>> TBCCR0 = clock.ticks_per_interrupt;
>>
>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>
>> /* Enable interrupts. */
>> __bis_SR_register(GIE);
>> Thanks,
>> Mike
>>
> --
> Thomas J. Grajewski
>
>
--
Thomas J. Grajewski
Reply by ●February 17, 20152015-02-17
Jake,
Interesting point. I have been watching @onestone abuse people for quite
some time. I thought I might interject a bit to see if I can stimulate his
cortisol levels ;) I love to do that to online bullies ;) I think it will
be fun to see his reaction.
From: "msp430@yahoogroups. com"
Reply-To: "msp430@yahoogroups. com"
Date: Tuesday, February 17, 2015 at 4:08 PM
To: "msp430@yahoogroups. com"
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Hi All,
First off, The first rule of software development is that the best code is
the one you didn't have to write ^^.
I agree with Al here, why aren't you using the build in UART tool in the
microprocessor. It is build to be used in this way, and the only reason ever
not to is if you have to use a certain chip and you have run out of UART
ports to use.
@Martin: Now you are just poking the bear aren't you.
Cheers,
Jake
On Tue, Feb 17, 2015 at 2:07 PM, Onestone o...@bigpond.net.au [msp430]
wrote:
>
>
>
>
>
>
> Why oh why are you bit banging this when the MSP430 has an extremely simple
> UART in hardware. Are interrupts that fightening?
>
> Al
>
>
> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>
>
>>
>>
>>
>>
>>
>>
>> Hello, I'm trying to communicate with my RF module through UART interface.
>> However, I get many errors even with low load. I suspect that I have an issue
>> with the way that I configure the clock or the UART.
>>
>>
>>
>>
>> Basically, for the UART functionality I use http://glitovsky.com/blog/?p00
>>
>>
>> (I configured the connection as 8N1 at 115200).
>>
>>
>>
>>
>>
>> The clock configuration below is used with MCLK = 25 MHz ( when I use it with
>> MCLK MHz I cannot communicate with the UART module at all ) .
>>
>>
>>
>>
>> P5SEL |= 0x0C;
>>
>>
>>
>> /* Select REF0 for FLL reference. */
>>
>>
>> UCSCTL3 &= ~SELREF_7;
>>
>>
>> UCSCTL3 |= SELREF_2;
>>
>>
>>
>>
>> /* Set ACLK to use REF0CLK.
>>
>>
>> * Set SMCLK to use the DCO.
>>
>>
>> */
>>
>>
>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>
>>
>>
>>
>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>
>>
>> /* Initialize FLL. */
>>
>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>
>>
>>
>>
>>
>> XT2_Start(XT2DRIVE_0);
>>
>>
>>
>>
>> UCSCTL4 &= ~SELA_7;
>>
>>
>> UCSCTL4 |= SELA_2;
>>
>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>>
>> /* Enable interrupt for TBCCR0. */
>>
>> TBCCTL0 = CCIE;
>>
>>
>>
>> /* Number of ticks per millisecond. */
>>
>> clock.aclk = 32768;
>>
>> clock.ticks_per_interrupt = clock.aclk / 1000;
>>
>> TBCCR0 = clock.ticks_per_interrupt;
>>
>>
>>
>>
>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>>
>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>
>>
>>
>>
>> /* Enable interrupts. */
>>
>> __bis_SR_register(GIE);
>>
>>
>>
>>
>>
>>
>> Thanks,
>>
>> Mike
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>
>
>
>
>
--
Thomas J. Grajewski
Interesting point. I have been watching @onestone abuse people for quite
some time. I thought I might interject a bit to see if I can stimulate his
cortisol levels ;) I love to do that to online bullies ;) I think it will
be fun to see his reaction.
From: "msp430@yahoogroups. com"
Reply-To: "msp430@yahoogroups. com"
Date: Tuesday, February 17, 2015 at 4:08 PM
To: "msp430@yahoogroups. com"
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Hi All,
First off, The first rule of software development is that the best code is
the one you didn't have to write ^^.
I agree with Al here, why aren't you using the build in UART tool in the
microprocessor. It is build to be used in this way, and the only reason ever
not to is if you have to use a certain chip and you have run out of UART
ports to use.
@Martin: Now you are just poking the bear aren't you.
Cheers,
Jake
On Tue, Feb 17, 2015 at 2:07 PM, Onestone o...@bigpond.net.au [msp430]
wrote:
>
>
>
>
>
>
> Why oh why are you bit banging this when the MSP430 has an extremely simple
> UART in hardware. Are interrupts that fightening?
>
> Al
>
>
> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>
>
>>
>>
>>
>>
>>
>>
>> Hello, I'm trying to communicate with my RF module through UART interface.
>> However, I get many errors even with low load. I suspect that I have an issue
>> with the way that I configure the clock or the UART.
>>
>>
>>
>>
>> Basically, for the UART functionality I use http://glitovsky.com/blog/?p00
>>
>>
>> (I configured the connection as 8N1 at 115200).
>>
>>
>>
>>
>>
>> The clock configuration below is used with MCLK = 25 MHz ( when I use it with
>> MCLK MHz I cannot communicate with the UART module at all ) .
>>
>>
>>
>>
>> P5SEL |= 0x0C;
>>
>>
>>
>> /* Select REF0 for FLL reference. */
>>
>>
>> UCSCTL3 &= ~SELREF_7;
>>
>>
>> UCSCTL3 |= SELREF_2;
>>
>>
>>
>>
>> /* Set ACLK to use REF0CLK.
>>
>>
>> * Set SMCLK to use the DCO.
>>
>>
>> */
>>
>>
>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>
>>
>>
>>
>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>
>>
>> /* Initialize FLL. */
>>
>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>
>>
>>
>>
>>
>> XT2_Start(XT2DRIVE_0);
>>
>>
>>
>>
>> UCSCTL4 &= ~SELA_7;
>>
>>
>> UCSCTL4 |= SELA_2;
>>
>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>>
>> /* Enable interrupt for TBCCR0. */
>>
>> TBCCTL0 = CCIE;
>>
>>
>>
>> /* Number of ticks per millisecond. */
>>
>> clock.aclk = 32768;
>>
>> clock.ticks_per_interrupt = clock.aclk / 1000;
>>
>> TBCCR0 = clock.ticks_per_interrupt;
>>
>>
>>
>>
>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>>
>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>
>>
>>
>>
>> /* Enable interrupts. */
>>
>> __bis_SR_register(GIE);
>>
>>
>>
>>
>>
>>
>> Thanks,
>>
>> Mike
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>
>
>
>
>
--
Thomas J. Grajewski
Reply by ●February 17, 20152015-02-17
Look at the bottom of this email for unsubscribing instructions.
Emmett Redd Ph.D. mailto:E...@missouristate.edu
Professor (417)836-5221
Department of Physics, Astronomy, and Materials Science
Missouri State University Fax (417)836-6226
901 SOUTH NATIONAL Lab (417)836-3770
SPRINGFIELD, MO 65897 USA Dept (417)836-5131
In statesmanship get the formalities right, never mind about the moralities. -- Mark Twain.
________________________________________
From: m... [m...]
Sent: Tuesday, February 17, 2015 5:19 PM
To: m...
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Guys please, I started getting a lot of your discussion emails from you , how can I stop this , I mean to Unsubscribe from this msp430 group??????????
On Tuesday, February 17, 2015 3:17 PM, "Onestone o...@bigpond.net.au [msp430]" wrote:
Wouldn't help, the problem is further up, and a lower body transplant could be risky, I might end up with boobs or something! Hmmm! thinking on it would that be So bad?
Al
On 18/02/2015 9:38 AM, Jake Grajewski p...@gmail.com [msp430] wrote:
or get new hands ^^
On Tue, Feb 17, 2015 at 3:02 PM, Onestone o...@bigpond.net.au [msp430] > wrote:
Well typing can be difficult when you only have limited use of your hands. I'll try to do better next time.
Al
On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com [msp430] wrote:
I believe you were looking for frightening not fightening".
From: "msp430@yahoogroups. com" >
Reply-To: "msp430@yahoogroups. com" >
Date: Tuesday, February 17, 2015 at 3:07 PM
To: "msp430@yahoogroups. com" >
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Why oh why are you bit banging this when the MSP430 has an extremely simple UART in hardware. Are interrupts that fightening?
Al
On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
Hello, I'm trying to communicate with my RF module through UART interface. However, I get many errors even with low load. I suspect that I have an issue with the way that I configure the clock or the UART.
Basically, for the UART functionality I use http://glitovsky.com/blog/?p=300
(I configured the connection as 8N1 at 115200).
The clock configuration below is used with MCLK = 25 MHz ( when I use it with MCLK=16 MHz I cannot communicate with the UART module at all ) .
P5SEL |= 0x0C;
/* Select REF0 for FLL reference. */
UCSCTL3 &= ~SELREF_7;
UCSCTL3 |= SELREF_2;
/* Set ACLK to use REF0CLK.
* Set SMCLK to use the DCO.
*/
UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
/* Initialize FLL. */
Init_FLL_Settle(mclk/1000L, mclk/32768);
XT2_Start(XT2DRIVE_0);
UCSCTL4 &= ~SELA_7;
UCSCTL4 |= SELA_2;
UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
/* Enable interrupt for TBCCR0. */
TBCCTL0 = CCIE;
/* Number of ticks per millisecond. */
clock.aclk = 32768;
clock.ticks_per_interrupt = clock.aclk / 1000;
TBCCR0 = clock.ticks_per_interrupt;
/* Use ACLK, set timer to up-count mode, and start timer at zero. */
TBCTL = TBSSEL_1 | MC_2 | TBCLR;
/* Enable interrupts. */
__bis_SR_register(GIE);
Thanks,
Mike
--
Thomas J. Grajewski
Emmett Redd Ph.D. mailto:E...@missouristate.edu
Professor (417)836-5221
Department of Physics, Astronomy, and Materials Science
Missouri State University Fax (417)836-6226
901 SOUTH NATIONAL Lab (417)836-3770
SPRINGFIELD, MO 65897 USA Dept (417)836-5131
In statesmanship get the formalities right, never mind about the moralities. -- Mark Twain.
________________________________________
From: m... [m...]
Sent: Tuesday, February 17, 2015 5:19 PM
To: m...
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Guys please, I started getting a lot of your discussion emails from you , how can I stop this , I mean to Unsubscribe from this msp430 group??????????
On Tuesday, February 17, 2015 3:17 PM, "Onestone o...@bigpond.net.au [msp430]" wrote:
Wouldn't help, the problem is further up, and a lower body transplant could be risky, I might end up with boobs or something! Hmmm! thinking on it would that be So bad?
Al
On 18/02/2015 9:38 AM, Jake Grajewski p...@gmail.com [msp430] wrote:
or get new hands ^^
On Tue, Feb 17, 2015 at 3:02 PM, Onestone o...@bigpond.net.au [msp430] > wrote:
Well typing can be difficult when you only have limited use of your hands. I'll try to do better next time.
Al
On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com [msp430] wrote:
I believe you were looking for frightening not fightening".
From: "msp430@yahoogroups. com" >
Reply-To: "msp430@yahoogroups. com" >
Date: Tuesday, February 17, 2015 at 3:07 PM
To: "msp430@yahoogroups. com" >
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Why oh why are you bit banging this when the MSP430 has an extremely simple UART in hardware. Are interrupts that fightening?
Al
On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
Hello, I'm trying to communicate with my RF module through UART interface. However, I get many errors even with low load. I suspect that I have an issue with the way that I configure the clock or the UART.
Basically, for the UART functionality I use http://glitovsky.com/blog/?p=300
(I configured the connection as 8N1 at 115200).
The clock configuration below is used with MCLK = 25 MHz ( when I use it with MCLK=16 MHz I cannot communicate with the UART module at all ) .
P5SEL |= 0x0C;
/* Select REF0 for FLL reference. */
UCSCTL3 &= ~SELREF_7;
UCSCTL3 |= SELREF_2;
/* Set ACLK to use REF0CLK.
* Set SMCLK to use the DCO.
*/
UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
/* Initialize FLL. */
Init_FLL_Settle(mclk/1000L, mclk/32768);
XT2_Start(XT2DRIVE_0);
UCSCTL4 &= ~SELA_7;
UCSCTL4 |= SELA_2;
UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
/* Enable interrupt for TBCCR0. */
TBCCTL0 = CCIE;
/* Number of ticks per millisecond. */
clock.aclk = 32768;
clock.ticks_per_interrupt = clock.aclk / 1000;
TBCCR0 = clock.ticks_per_interrupt;
/* Use ACLK, set timer to up-count mode, and start timer at zero. */
TBCTL = TBSSEL_1 | MC_2 | TBCLR;
/* Enable interrupts. */
__bis_SR_register(GIE);
Thanks,
Mike
--
Thomas J. Grajewski
Reply by ●February 17, 20152015-02-17
IMHO he only abuses the people that deserve it, aka the school room trolls
who want us to get their degrees for them.
It is true there are no dumb question, yet there are some that you can
easily figure out yourself and shouldn't bug people by asking them. I would
go on further to say that this is a condition brought on by the "google"
age, where people do not need to learn anything if they can simply google
it. We are seeing an over reliance on internet resources instead of people
fully understanding the concept.
Just my 2 cents.
Cheers,
Jake
On Tue, Feb 17, 2015 at 3:21 PM, Martin Bruner M...@bruner-consulting.com
[msp430] wrote:
> Jake,
>
> Interesting point. I have been watching @onestone abuse people for quite
> some time. I thought I might interject a bit to see if I can stimulate his
> cortisol levels ;) I love to do that to online bullies ;) I think it will
> be fun to see his reaction….
>
> From: "msp430@yahoogroups. com"
> Reply-To: "msp430@yahoogroups. com"
> Date: Tuesday, February 17, 2015 at 4:08 PM
> To: "msp430@yahoogroups. com"
> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>
> Hi All,
>
> First off, The first rule of software development is that the best code is
> the one you didn't have to write ^^.
>
> I agree with Al here, why aren't you using the build in UART tool in the
> microprocessor. It is build to be used in this way, and the only reason
> ever not to is if you have to use a certain chip and you have run out of
> UART ports to use.
>
> @Martin: Now you are just poking the bear aren't you.
>
> Cheers,
> Jake
>
> On Tue, Feb 17, 2015 at 2:07 PM, Onestone o...@bigpond.net.au
> [msp430] wrote:
>
>> Why oh why are you bit banging this when the MSP430 has an extremely
>> simple UART in hardware. Are interrupts that fightening?
>>
>> Al
>> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>> Hello, I'm trying to communicate with my RF module through UART
>> interface. However, I get many errors even with low load. I suspect that
>> I have an issue with the way that I configure the clock or the UART.
>> Basically, for the UART functionality I use
>> http://glitovsky.com/blog/?p00
>>
>> (I configured the connection as 8N1 at 115200).
>> The clock configuration below is used with MCLK = 25 MHz ( when I use
>> it with MCLK MHz I cannot communicate with the UART module at all ) .
>> P5SEL |= 0x0C;
>>
>> /* Select REF0 for FLL reference. */
>>
>> UCSCTL3 &= ~SELREF_7;
>>
>> UCSCTL3 |= SELREF_2;
>> /* Set ACLK to use REF0CLK.
>>
>> * Set SMCLK to use the DCO.
>>
>> */
>>
>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>
>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>> /* Initialize FLL. */
>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>
>> XT2_Start(XT2DRIVE_0);
>>
>> UCSCTL4 &= ~SELA_7;
>> UCSCTL4 |= SELA_2;
>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>> /* Enable interrupt for TBCCR0. */
>> TBCCTL0 = CCIE;
>>
>> /* Number of ticks per millisecond. */
>> clock.aclk = 32768;
>> clock.ticks_per_interrupt = clock.aclk / 1000;
>> TBCCR0 = clock.ticks_per_interrupt;
>>
>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>
>> /* Enable interrupts. */
>> __bis_SR_register(GIE);
>> Thanks,
>> Mike
>>
> --
> Thomas J. Grajewski
>
>
>
--
Thomas J. Grajewski
who want us to get their degrees for them.
It is true there are no dumb question, yet there are some that you can
easily figure out yourself and shouldn't bug people by asking them. I would
go on further to say that this is a condition brought on by the "google"
age, where people do not need to learn anything if they can simply google
it. We are seeing an over reliance on internet resources instead of people
fully understanding the concept.
Just my 2 cents.
Cheers,
Jake
On Tue, Feb 17, 2015 at 3:21 PM, Martin Bruner M...@bruner-consulting.com
[msp430] wrote:
> Jake,
>
> Interesting point. I have been watching @onestone abuse people for quite
> some time. I thought I might interject a bit to see if I can stimulate his
> cortisol levels ;) I love to do that to online bullies ;) I think it will
> be fun to see his reaction….
>
> From: "msp430@yahoogroups. com"
> Reply-To: "msp430@yahoogroups. com"
> Date: Tuesday, February 17, 2015 at 4:08 PM
> To: "msp430@yahoogroups. com"
> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>
> Hi All,
>
> First off, The first rule of software development is that the best code is
> the one you didn't have to write ^^.
>
> I agree with Al here, why aren't you using the build in UART tool in the
> microprocessor. It is build to be used in this way, and the only reason
> ever not to is if you have to use a certain chip and you have run out of
> UART ports to use.
>
> @Martin: Now you are just poking the bear aren't you.
>
> Cheers,
> Jake
>
> On Tue, Feb 17, 2015 at 2:07 PM, Onestone o...@bigpond.net.au
> [msp430] wrote:
>
>> Why oh why are you bit banging this when the MSP430 has an extremely
>> simple UART in hardware. Are interrupts that fightening?
>>
>> Al
>> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>> Hello, I'm trying to communicate with my RF module through UART
>> interface. However, I get many errors even with low load. I suspect that
>> I have an issue with the way that I configure the clock or the UART.
>> Basically, for the UART functionality I use
>> http://glitovsky.com/blog/?p00
>>
>> (I configured the connection as 8N1 at 115200).
>> The clock configuration below is used with MCLK = 25 MHz ( when I use
>> it with MCLK MHz I cannot communicate with the UART module at all ) .
>> P5SEL |= 0x0C;
>>
>> /* Select REF0 for FLL reference. */
>>
>> UCSCTL3 &= ~SELREF_7;
>>
>> UCSCTL3 |= SELREF_2;
>> /* Set ACLK to use REF0CLK.
>>
>> * Set SMCLK to use the DCO.
>>
>> */
>>
>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>
>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>> /* Initialize FLL. */
>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>
>> XT2_Start(XT2DRIVE_0);
>>
>> UCSCTL4 &= ~SELA_7;
>> UCSCTL4 |= SELA_2;
>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>> /* Enable interrupt for TBCCR0. */
>> TBCCTL0 = CCIE;
>>
>> /* Number of ticks per millisecond. */
>> clock.aclk = 32768;
>> clock.ticks_per_interrupt = clock.aclk / 1000;
>> TBCCR0 = clock.ticks_per_interrupt;
>>
>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>
>> /* Enable interrupts. */
>> __bis_SR_register(GIE);
>> Thanks,
>> Mike
>>
> --
> Thomas J. Grajewski
>
>
>
--
Thomas J. Grajewski
Reply by ●February 17, 20152015-02-17
Who's bullying, I'm pointing out a simple fact, and asking a valid
question, over the years I've been in this group one point seems to
dominate here. The vast majorioty of people are scared of using
interrupts, especially C programmers.
Bullying requires some form of abuse. Get your facts right before you
make pointless off topic comments.
Al
On 18/02/2015 9:46 AM, Martin Bruner M...@bruner-consulting.com
[msp430] wrote:
> Spelling is important when bullying someone online.
>
> From: "msp430@yahoogroups. com" > >
> Reply-To: "msp430@yahoogroups. com" > >
> Date: Tuesday, February 17, 2015 at 4:02 PM
> To: "msp430@yahoogroups. com" > >
> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>
> Well typing can be difficult when you only have limited use of your
> hands. I'll try to do better next time.
>
> Al
> On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com
> [msp430] wrote:
>> I believe you were looking for “frightening” not “fightening".
>>
>> From: "msp430@yahoogroups. com" >> >
>> Reply-To: "msp430@yahoogroups. com" >> >
>> Date: Tuesday, February 17, 2015 at 3:07 PM
>> To: "msp430@yahoogroups. com" >> >
>> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>>
>> Why oh why are you bit banging this when the MSP430 has an extremely
>> simple UART in hardware. Are interrupts that fightening?
>>
>> Al
>>
>> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>>>
>>>
>>>
>>> Hello, I'm trying to communicate with my RF module through UART
>>> interface. However, I get many errors even with low load. I suspect
>>> that I have an issue with the way that I configure the clock or the
>>> UART.
>>>
>>>
>>> Basically, for the UART functionality I use
>>> http://glitovsky.com/blog/?p00
>>>
>>> (I configured the connection as 8N1 at 115200).
>>>
>>>
>>> The clock configuration below is used with MCLK = 25 MHz ( when I
>>> use it with MCLK MHz I cannot communicate with the UART module at
>>> all ) .
>>>
>>>
>>> P5SEL |= 0x0C;
>>>
>>> /* Select REF0 for FLL reference. */
>>>
>>> UCSCTL3 &= ~SELREF_7;
>>>
>>> UCSCTL3 |= SELREF_2;
>>>
>>>
>>> /* Set ACLK to use REF0CLK.
>>>
>>> * Set SMCLK to use the DCO.
>>>
>>> */
>>>
>>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>>
>>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>>
>>> /* Initialize FLL. */
>>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>>
>>> XT2_Start(XT2DRIVE_0);
>>>
>>> UCSCTL4 &= ~SELA_7;
>>> UCSCTL4 |= SELA_2;
>>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>>> /* Enable interrupt for TBCCR0. */
>>> TBCCTL0 = CCIE;
>>> /* Number of ticks per millisecond. */
>>> clock.aclk = 32768;
>>> clock.ticks_per_interrupt = clock.aclk / 1000;
>>> TBCCR0 = clock.ticks_per_interrupt;
>>>
>>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>>
>>> /* Enable interrupts. */
>>> __bis_SR_register(GIE);
>>> Thanks,
>>> Mike
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>
question, over the years I've been in this group one point seems to
dominate here. The vast majorioty of people are scared of using
interrupts, especially C programmers.
Bullying requires some form of abuse. Get your facts right before you
make pointless off topic comments.
Al
On 18/02/2015 9:46 AM, Martin Bruner M...@bruner-consulting.com
[msp430] wrote:
> Spelling is important when bullying someone online.
>
> From: "msp430@yahoogroups. com" > >
> Reply-To: "msp430@yahoogroups. com" > >
> Date: Tuesday, February 17, 2015 at 4:02 PM
> To: "msp430@yahoogroups. com" > >
> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>
> Well typing can be difficult when you only have limited use of your
> hands. I'll try to do better next time.
>
> Al
> On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com
> [msp430] wrote:
>> I believe you were looking for “frightening” not “fightening".
>>
>> From: "msp430@yahoogroups. com" >> >
>> Reply-To: "msp430@yahoogroups. com" >> >
>> Date: Tuesday, February 17, 2015 at 3:07 PM
>> To: "msp430@yahoogroups. com" >> >
>> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>>
>> Why oh why are you bit banging this when the MSP430 has an extremely
>> simple UART in hardware. Are interrupts that fightening?
>>
>> Al
>>
>> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>>>
>>>
>>>
>>> Hello, I'm trying to communicate with my RF module through UART
>>> interface. However, I get many errors even with low load. I suspect
>>> that I have an issue with the way that I configure the clock or the
>>> UART.
>>>
>>>
>>> Basically, for the UART functionality I use
>>> http://glitovsky.com/blog/?p00
>>>
>>> (I configured the connection as 8N1 at 115200).
>>>
>>>
>>> The clock configuration below is used with MCLK = 25 MHz ( when I
>>> use it with MCLK MHz I cannot communicate with the UART module at
>>> all ) .
>>>
>>>
>>> P5SEL |= 0x0C;
>>>
>>> /* Select REF0 for FLL reference. */
>>>
>>> UCSCTL3 &= ~SELREF_7;
>>>
>>> UCSCTL3 |= SELREF_2;
>>>
>>>
>>> /* Set ACLK to use REF0CLK.
>>>
>>> * Set SMCLK to use the DCO.
>>>
>>> */
>>>
>>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>>
>>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>>
>>> /* Initialize FLL. */
>>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>>
>>> XT2_Start(XT2DRIVE_0);
>>>
>>> UCSCTL4 &= ~SELA_7;
>>> UCSCTL4 |= SELA_2;
>>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>>> /* Enable interrupt for TBCCR0. */
>>> TBCCTL0 = CCIE;
>>> /* Number of ticks per millisecond. */
>>> clock.aclk = 32768;
>>> clock.ticks_per_interrupt = clock.aclk / 1000;
>>> TBCCR0 = clock.ticks_per_interrupt;
>>>
>>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>>
>>> /* Enable interrupts. */
>>> __bis_SR_register(GIE);
>>> Thanks,
>>> Mike
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>
Reply by ●February 17, 20152015-02-17
tested by whom? do you trust just anybody to develop libraries. Ti
rarely get it right, and they should be the goto people. In this
specific example the guy who posted the UART example code actually
states that it is untested.
Al
On 18/02/2015 9:51 AM, Jake Grajewski p...@gmail.com [msp430] wrote:
> Touche, but a good software developer /*never */uses untested
> libraries, now that would just be silly. ;-P.
>
> Caption this picture
>
> On Tue, Feb 17, 2015 at 3:15 PM, Onestone o...@bigpond.net.au
> [msp430] > > wrote:
>
> Wrong, totally. the first rule of software development is that the
> best code is the one that you personally know has been fully
> debugged, and usually that is one that you wrote. If you trust
> others to write better code than you then you are asking for a
> world of grief.
>
> Who says I'm a bear? Anyway it's 'built in' not 'build in'. :-P
>
> Al
>
> On 18/02/2015 9:38 AM, Jake Grajewski p...@gmail.com
> [msp430] wrote:
>> Hi All,
>>
>> First off, The first rule of software development is that the
>> best code is the one you didn't have to write ^^.
>>
>> I agree with Al here, why aren't you using the build in UART tool
>> in the microprocessor. It is build to be used in this way, and
>> the only reason ever not to is if you have to use a certain chip
>> and you have run out of UART ports to use.
>>
>> @Martin: Now you are just poking the bear aren't you.
>>
>> Cheers,
>> Jake
>>
>> On Tue, Feb 17, 2015 at 2:07 PM, Onestone o...@bigpond.net.au
>> [msp430] >> > wrote:
>>
>> Why oh why are you bit banging this when the MSP430 has an
>> extremely simple UART in hardware. Are interrupts that
>> fightening?
>>
>> Al
>>
>> On 18/02/2015 2:21 AM, m...@yahoo.com
>> [msp430] wrote:
>>>
>>>
>>>
>>> Hello, I'm trying to communicate with my RF module through
>>> UART interface. However, I get many errors even with low
>>> load. I suspect that I have an issue with the way that I
>>> configure the clock or the UART.
>>>
>>>
>>> Basically, for the UART functionality I use
>>> http://glitovsky.com/blog/?p00
>>>
>>> (I configured the connection as 8N1 at 115200).
>>>
>>>
>>> The clock configuration below is used with MCLK = 25 MHz (
>>> when I use it with MCLK MHz I cannot communicate with the
>>> UART module at all ) .
>>>
>>>
>>> P5SEL |= 0x0C;
>>>
>>> /* Select REF0 for FLL reference. */
>>>
>>> UCSCTL3 &= ~SELREF_7;
>>>
>>> UCSCTL3 |= SELREF_2;
>>>
>>>
>>> /* Set ACLK to use REF0CLK.
>>>
>>> * Set SMCLK to use the DCO.
>>>
>>> */
>>>
>>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>>
>>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>>
>>> /* Initialize FLL. */
>>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>>
>>> XT2_Start(XT2DRIVE_0);
>>>
>>> UCSCTL4 &= ~SELA_7;
>>> UCSCTL4 |= SELA_2;
>>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>>> /* Enable interrupt for TBCCR0. */
>>> TBCCTL0 = CCIE;
>>> /* Number of ticks per millisecond. */
>>> clock.aclk = 32768;
>>> clock.ticks_per_interrupt = clock.aclk / 1000;
>>> TBCCR0 = clock.ticks_per_interrupt;
>>>
>>> /* Use ACLK, set timer to up-count mode, and start timer
>>> at zero. */
>>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>>
>>> /* Enable interrupts. */
>>> __bis_SR_register(GIE);
>>> Thanks,
>>> Mike
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>> --
>> Thomas J. Grajewski
>>
> --
> Thomas J. Grajewski
rarely get it right, and they should be the goto people. In this
specific example the guy who posted the UART example code actually
states that it is untested.
Al
On 18/02/2015 9:51 AM, Jake Grajewski p...@gmail.com [msp430] wrote:
> Touche, but a good software developer /*never */uses untested
> libraries, now that would just be silly. ;-P.
>
> Caption this picture
>
> On Tue, Feb 17, 2015 at 3:15 PM, Onestone o...@bigpond.net.au
> [msp430] > > wrote:
>
> Wrong, totally. the first rule of software development is that the
> best code is the one that you personally know has been fully
> debugged, and usually that is one that you wrote. If you trust
> others to write better code than you then you are asking for a
> world of grief.
>
> Who says I'm a bear? Anyway it's 'built in' not 'build in'. :-P
>
> Al
>
> On 18/02/2015 9:38 AM, Jake Grajewski p...@gmail.com
> [msp430] wrote:
>> Hi All,
>>
>> First off, The first rule of software development is that the
>> best code is the one you didn't have to write ^^.
>>
>> I agree with Al here, why aren't you using the build in UART tool
>> in the microprocessor. It is build to be used in this way, and
>> the only reason ever not to is if you have to use a certain chip
>> and you have run out of UART ports to use.
>>
>> @Martin: Now you are just poking the bear aren't you.
>>
>> Cheers,
>> Jake
>>
>> On Tue, Feb 17, 2015 at 2:07 PM, Onestone o...@bigpond.net.au
>> [msp430] >> > wrote:
>>
>> Why oh why are you bit banging this when the MSP430 has an
>> extremely simple UART in hardware. Are interrupts that
>> fightening?
>>
>> Al
>>
>> On 18/02/2015 2:21 AM, m...@yahoo.com
>> [msp430] wrote:
>>>
>>>
>>>
>>> Hello, I'm trying to communicate with my RF module through
>>> UART interface. However, I get many errors even with low
>>> load. I suspect that I have an issue with the way that I
>>> configure the clock or the UART.
>>>
>>>
>>> Basically, for the UART functionality I use
>>> http://glitovsky.com/blog/?p00
>>>
>>> (I configured the connection as 8N1 at 115200).
>>>
>>>
>>> The clock configuration below is used with MCLK = 25 MHz (
>>> when I use it with MCLK MHz I cannot communicate with the
>>> UART module at all ) .
>>>
>>>
>>> P5SEL |= 0x0C;
>>>
>>> /* Select REF0 for FLL reference. */
>>>
>>> UCSCTL3 &= ~SELREF_7;
>>>
>>> UCSCTL3 |= SELREF_2;
>>>
>>>
>>> /* Set ACLK to use REF0CLK.
>>>
>>> * Set SMCLK to use the DCO.
>>>
>>> */
>>>
>>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>>
>>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>>
>>> /* Initialize FLL. */
>>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>>
>>> XT2_Start(XT2DRIVE_0);
>>>
>>> UCSCTL4 &= ~SELA_7;
>>> UCSCTL4 |= SELA_2;
>>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>>> /* Enable interrupt for TBCCR0. */
>>> TBCCTL0 = CCIE;
>>> /* Number of ticks per millisecond. */
>>> clock.aclk = 32768;
>>> clock.ticks_per_interrupt = clock.aclk / 1000;
>>> TBCCR0 = clock.ticks_per_interrupt;
>>>
>>> /* Use ACLK, set timer to up-count mode, and start timer
>>> at zero. */
>>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>>
>>> /* Enable interrupts. */
>>> __bis_SR_register(GIE);
>>> Thanks,
>>> Mike
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>> --
>> Thomas J. Grajewski
>>
> --
> Thomas J. Grajewski
Reply by ●February 17, 20152015-02-17
I love getting under your skin. Maybe troll would be more accurate. I bet
you are waiting for me to reply as your blood pressure goes up. Maybe I
will answer your next email and maybe not You never know troll
From: "msp430@yahoogroups. com"
Reply-To: "msp430@yahoogroups. com"
Date: Tuesday, February 17, 2015 at 4:28 PM
To: "msp430@yahoogroups. com"
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Who's bullying, I'm pointing out a simple fact, and asking a valid
question, over the years I've been in this group one point seems to dominate
here. The vast majorioty of people are scared of using interrupts,
especially C programmers.
Bullying requires some form of abuse. Get your facts right before you make
pointless off topic comments.
Al
On 18/02/2015 9:46 AM, Martin Bruner M...@bruner-consulting.com [msp430]
wrote:
>
>
>
> Spelling is important when bullying someone online.
>
>
>
>
> From: "msp430@yahoogroups. com"
>
> Reply-To: "msp430@yahoogroups. com"
>
> Date: Tuesday, February 17, 2015 at 4:02 PM
> To: "msp430@yahoogroups. com"
>
> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>
>
>
>
>
>
>
>
>
> Well typing can be difficult when you only have limited use of your hands.
> I'll try to do better next time.
>
> Al
>
>
>
>
> On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com [msp430]
> wrote:
>
>
>>
>>
>>
>> I believe you were looking for frightening not fightening".
>>
>>
>>
>>
>> From: "msp430@yahoogroups. com"
>>
>> Reply-To: "msp430@yahoogroups. com"
>>
>> Date: Tuesday, February 17, 2015 at 3:07 PM
>> To: "msp430@yahoogroups. com"
>>
>> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> Why oh why are you bit banging this when the MSP430 has an extremely simple
>> UART in hardware. Are interrupts that fightening?
>>
>> Al
>>
>>
>>
>> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>>
>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> Hello, I'm trying to communicate with my RF module through UART interface.
>>> However, I get many errors even with low load. I suspect that I have an
>>> issue with the way that I configure the clock or the UART.
>>>
>>>
>>>
>>>
>>>
>>>
>>> Basically, for the UART functionality I use http://glitovsky.com/blog/?p00
>>>
>>>
>>> (I configured the connection as 8N1 at 115200).
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> The clock configuration below is used with MCLK = 25 MHz ( when I use it
>>> with MCLK MHz I cannot communicate with the UART module at all ) .
>>>
>>>
>>>
>>>
>>>
>>>
>>> P5SEL |= 0x0C;
>>>
>>>
>>>
>>> /* Select REF0 for FLL reference. */
>>>
>>>
>>> UCSCTL3 &= ~SELREF_7;
>>>
>>>
>>> UCSCTL3 |= SELREF_2;
>>>
>>>
>>>
>>>
>>>
>>>
>>> /* Set ACLK to use REF0CLK.
>>>
>>>
>>> * Set SMCLK to use the DCO.
>>>
>>>
>>> */
>>>
>>>
>>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>>
>>>
>>>
>>>
>>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>>
>>>
>>> /* Initialize FLL. */
>>>
>>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>>
>>>
>>>
>>>
>>>
>>> XT2_Start(XT2DRIVE_0);
>>>
>>>
>>>
>>>
>>> UCSCTL4 &= ~SELA_7;
>>>
>>>
>>> UCSCTL4 |= SELA_2;
>>>
>>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>>>
>>> /* Enable interrupt for TBCCR0. */
>>>
>>> TBCCTL0 = CCIE;
>>>
>>>
>>>
>>> /* Number of ticks per millisecond. */
>>>
>>> clock.aclk = 32768;
>>>
>>> clock.ticks_per_interrupt = clock.aclk / 1000;
>>>
>>> TBCCR0 = clock.ticks_per_interrupt;
>>>
>>>
>>>
>>>
>>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>>>
>>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>>
>>>
>>>
>>>
>>> /* Enable interrupts. */
>>>
>>> __bis_SR_register(GIE);
>>>
>>>
>>>
>>>
>>>
>>>
>>> Thanks,
>>>
>>> Mike
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>
>>
>>
>>
>>
>>
>>
>
>
>
>
>
>
>
>
you are waiting for me to reply as your blood pressure goes up. Maybe I
will answer your next email and maybe not You never know troll
From: "msp430@yahoogroups. com"
Reply-To: "msp430@yahoogroups. com"
Date: Tuesday, February 17, 2015 at 4:28 PM
To: "msp430@yahoogroups. com"
Subject: Re: [msp430] MSP430F5528 - Clock and UART
Who's bullying, I'm pointing out a simple fact, and asking a valid
question, over the years I've been in this group one point seems to dominate
here. The vast majorioty of people are scared of using interrupts,
especially C programmers.
Bullying requires some form of abuse. Get your facts right before you make
pointless off topic comments.
Al
On 18/02/2015 9:46 AM, Martin Bruner M...@bruner-consulting.com [msp430]
wrote:
>
>
>
> Spelling is important when bullying someone online.
>
>
>
>
> From: "msp430@yahoogroups. com"
>
> Reply-To: "msp430@yahoogroups. com"
>
> Date: Tuesday, February 17, 2015 at 4:02 PM
> To: "msp430@yahoogroups. com"
>
> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>
>
>
>
>
>
>
>
>
> Well typing can be difficult when you only have limited use of your hands.
> I'll try to do better next time.
>
> Al
>
>
>
>
> On 18/02/2015 8:46 AM, Martin Bruner M...@bruner-consulting.com [msp430]
> wrote:
>
>
>>
>>
>>
>> I believe you were looking for frightening not fightening".
>>
>>
>>
>>
>> From: "msp430@yahoogroups. com"
>>
>> Reply-To: "msp430@yahoogroups. com"
>>
>> Date: Tuesday, February 17, 2015 at 3:07 PM
>> To: "msp430@yahoogroups. com"
>>
>> Subject: Re: [msp430] MSP430F5528 - Clock and UART
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> Why oh why are you bit banging this when the MSP430 has an extremely simple
>> UART in hardware. Are interrupts that fightening?
>>
>> Al
>>
>>
>>
>> On 18/02/2015 2:21 AM, m...@yahoo.com [msp430] wrote:
>>
>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> Hello, I'm trying to communicate with my RF module through UART interface.
>>> However, I get many errors even with low load. I suspect that I have an
>>> issue with the way that I configure the clock or the UART.
>>>
>>>
>>>
>>>
>>>
>>>
>>> Basically, for the UART functionality I use http://glitovsky.com/blog/?p00
>>>
>>>
>>> (I configured the connection as 8N1 at 115200).
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>> The clock configuration below is used with MCLK = 25 MHz ( when I use it
>>> with MCLK MHz I cannot communicate with the UART module at all ) .
>>>
>>>
>>>
>>>
>>>
>>>
>>> P5SEL |= 0x0C;
>>>
>>>
>>>
>>> /* Select REF0 for FLL reference. */
>>>
>>>
>>> UCSCTL3 &= ~SELREF_7;
>>>
>>>
>>> UCSCTL3 |= SELREF_2;
>>>
>>>
>>>
>>>
>>>
>>>
>>> /* Set ACLK to use REF0CLK.
>>>
>>>
>>> * Set SMCLK to use the DCO.
>>>
>>>
>>> */
>>>
>>>
>>> UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
>>>
>>>
>>>
>>>
>>> UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
>>>
>>>
>>> /* Initialize FLL. */
>>>
>>> Init_FLL_Settle(mclk/1000L, mclk/32768);
>>>
>>>
>>>
>>>
>>>
>>> XT2_Start(XT2DRIVE_0);
>>>
>>>
>>>
>>>
>>> UCSCTL4 &= ~SELA_7;
>>>
>>>
>>> UCSCTL4 |= SELA_2;
>>>
>>> UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
>>>
>>> /* Enable interrupt for TBCCR0. */
>>>
>>> TBCCTL0 = CCIE;
>>>
>>>
>>>
>>> /* Number of ticks per millisecond. */
>>>
>>> clock.aclk = 32768;
>>>
>>> clock.ticks_per_interrupt = clock.aclk / 1000;
>>>
>>> TBCCR0 = clock.ticks_per_interrupt;
>>>
>>>
>>>
>>>
>>> /* Use ACLK, set timer to up-count mode, and start timer at zero. */
>>>
>>> TBCTL = TBSSEL_1 | MC_2 | TBCLR;
>>>
>>>
>>>
>>>
>>> /* Enable interrupts. */
>>>
>>> __bis_SR_register(GIE);
>>>
>>>
>>>
>>>
>>>
>>>
>>> Thanks,
>>>
>>> Mike
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>
>>
>>
>>
>>
>>
>>
>
>
>
>
>
>
>
>
Reply by ●February 18, 20152015-02-18
Guys,
Thanks for getting back to me on this :)
I'm pretty new to MSP430, I did go over the UART lib code and I am familiar with how it works, I couldn't find any issue with it though. However, I might have missed something there.
I am using UART in hardware, the ports that I'm using is P3.3,4 = USCI_A0 TXD/RXD
Any chance you guys could point me to something that you are familiar with and know it works?
BTW, you guys are right and I wouldn't use untrusted *close* source. In this case though, the code is open and can be tested and inspected.
Mike
---In m..., wrote :
tested by whom? do you trust just anybody to develop libraries. Ti rarely get it right, and they should be the goto people. In this specific example the guy who posted the UART example code actually states that it is untested.
Al
On 18/02/2015 9:51 AM, Jake Grajewski prs.jake@... mailto:prs.jake@... [msp430] wrote:
Touche, but a good software developer never uses untested libraries, now that would just be silly. ;-P.
On Tue, Feb 17, 2015 at 3:15 PM, Onestone onestone@... mailto:onestone@... [msp430] wrote:
Wrong, totally. the first rule of software development is that the best code is the one that you personally know has been fully debugged, and usually that is one that you wrote. If you trust others to write better code than you then you are asking for a world of grief.
Who says I'm a bear? Anyway it's 'built in' not 'build in'. :-P
Al
On 18/02/2015 9:38 AM, Jake Grajewski prs.jake@... mailto:prs.jake@... [msp430] wrote:
Hi All,
First off, The first rule of software development is that the best code is the one you didn't have to write ^^.
I agree with Al here, why aren't you using the build in UART tool in the microprocessor. It is build to be used in this way, and the only reason ever not to is if you have to use a certain chip and you have run out of UART ports to use.
@Martin: Now you are just poking the bear aren't you.
Cheers,
Jake
On Tue, Feb 17, 2015 at 2:07 PM, Onestone onestone@... mailto:onestone@... [msp430] wrote:
Why oh why are you bit banging this when the MSP430 has an extremely simple UART in hardware. Are interrupts that fightening?
Al
On 18/02/2015 2:21 AM, mikemalgin@... mailto:mikemalgin@... [msp430] wrote:
Hello, I'm trying to communicate with my RF module through UART interface. However, I get many errors even with low load. I suspect that I have an issue with the way that I configure the clock or the UART.
Basically, for the UART functionality I use http://glitovsky.com/blog/?p00 http://glitovsky.com/blog/?p00
(I configured the connection as 8N1at 115200).
The clock configuration below is used with MCLK = 25 MHz ( when I use it with MCLK MHz I cannot communicate with the UART module at all ) .
P5SEL |= 0x0C;
/* Select REF0 for FLL reference. */
UCSCTL3 &= ~SELREF_7;
UCSCTL3 |= SELREF_2;
/* Set ACLK to use REF0CLK.
* Set SMCLK to use the DCO.
*/
UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
/* Initialize FLL. */
Init_FLL_Settle(mclk/1000L, mclk/32768);
XT2_Start(XT2DRIVE_0);
UCSCTL4 &= ~SELA_7;
UCSCTL4 |= SELA_2;
UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
/* Enable interrupt for TBCCR0. */
TBCCTL0 = CCIE;
/* Number of ticks per millisecond. */
clock.aclk = 32768;
clock.ticks_per_interrupt = clock.aclk / 1000;
TBCCR0 = clock.ticks_per_interrupt;
/* Use ACLK, set timer to up-count mode, and start timer at zero. */
TBCTL = TBSSEL_1 | MC_2 | TBCLR;
/* Enable interrupts. */
__bis_SR_register(GIE);
Thanks,
Mike
--
Thomas J. Grajewski
--
Thomas J. Grajewski
Thanks for getting back to me on this :)
I'm pretty new to MSP430, I did go over the UART lib code and I am familiar with how it works, I couldn't find any issue with it though. However, I might have missed something there.
I am using UART in hardware, the ports that I'm using is P3.3,4 = USCI_A0 TXD/RXD
Any chance you guys could point me to something that you are familiar with and know it works?
BTW, you guys are right and I wouldn't use untrusted *close* source. In this case though, the code is open and can be tested and inspected.
Mike
---In m..., wrote :
tested by whom? do you trust just anybody to develop libraries. Ti rarely get it right, and they should be the goto people. In this specific example the guy who posted the UART example code actually states that it is untested.
Al
On 18/02/2015 9:51 AM, Jake Grajewski prs.jake@... mailto:prs.jake@... [msp430] wrote:
Touche, but a good software developer never uses untested libraries, now that would just be silly. ;-P.
On Tue, Feb 17, 2015 at 3:15 PM, Onestone onestone@... mailto:onestone@... [msp430] wrote:
Wrong, totally. the first rule of software development is that the best code is the one that you personally know has been fully debugged, and usually that is one that you wrote. If you trust others to write better code than you then you are asking for a world of grief.
Who says I'm a bear? Anyway it's 'built in' not 'build in'. :-P
Al
On 18/02/2015 9:38 AM, Jake Grajewski prs.jake@... mailto:prs.jake@... [msp430] wrote:
Hi All,
First off, The first rule of software development is that the best code is the one you didn't have to write ^^.
I agree with Al here, why aren't you using the build in UART tool in the microprocessor. It is build to be used in this way, and the only reason ever not to is if you have to use a certain chip and you have run out of UART ports to use.
@Martin: Now you are just poking the bear aren't you.
Cheers,
Jake
On Tue, Feb 17, 2015 at 2:07 PM, Onestone onestone@... mailto:onestone@... [msp430] wrote:
Why oh why are you bit banging this when the MSP430 has an extremely simple UART in hardware. Are interrupts that fightening?
Al
On 18/02/2015 2:21 AM, mikemalgin@... mailto:mikemalgin@... [msp430] wrote:
Hello, I'm trying to communicate with my RF module through UART interface. However, I get many errors even with low load. I suspect that I have an issue with the way that I configure the clock or the UART.
Basically, for the UART functionality I use http://glitovsky.com/blog/?p00 http://glitovsky.com/blog/?p00
(I configured the connection as 8N1at 115200).
The clock configuration below is used with MCLK = 25 MHz ( when I use it with MCLK MHz I cannot communicate with the UART module at all ) .
P5SEL |= 0x0C;
/* Select REF0 for FLL reference. */
UCSCTL3 &= ~SELREF_7;
UCSCTL3 |= SELREF_2;
/* Set ACLK to use REF0CLK.
* Set SMCLK to use the DCO.
*/
UCSCTL4 &= ~SELA_7 & ~SELS_7 & ~SELM_7;
UCSCTL4 |= SELA_2 | SELS_4 | SELM_4;
/* Initialize FLL. */
Init_FLL_Settle(mclk/1000L, mclk/32768);
XT2_Start(XT2DRIVE_0);
UCSCTL4 &= ~SELA_7;
UCSCTL4 |= SELA_2;
UCSCTL8 |= SMCLKREQEN | MCLKREQEN | ACLKREQEN;
/* Enable interrupt for TBCCR0. */
TBCCTL0 = CCIE;
/* Number of ticks per millisecond. */
clock.aclk = 32768;
clock.ticks_per_interrupt = clock.aclk / 1000;
TBCCR0 = clock.ticks_per_interrupt;
/* Use ACLK, set timer to up-count mode, and start timer at zero. */
TBCTL = TBSSEL_1 | MC_2 | TBCLR;
/* Enable interrupts. */
__bis_SR_register(GIE);
Thanks,
Mike
--
Thomas J. Grajewski
--
Thomas J. Grajewski
