On Fri, 18 Sep 2015 09:44:06 -0500, you wrote:
> But, Jon's SLAA024 has this:
>
> If the interrupt is requested during the low power modes 3
> or 4, then additional two cycles are needed.
Your discovery, here, of the two additional cycles for the
interrupt accounts exactly for the 22 vs 20 cycles regarding
the LED itself.
and, the table on page 9-24, section 9.3.1, that I earlier
also pointed out on SLAA0024 which makes it explicit in my
own view that one of your instructions requires 5 cycles, not
4 ...
It looks like together we may have accounted for three of the
four cycles you are seeing.
Not perfect. But not bad. Narrowing in on the observations,
at least.
Jon
Posted by: Jon Kirwan
SD24 to sample a resistive bridge with pulsed bridge supply
Started by ●September 9, 2015
Reply by ●September 18, 20152015-09-18
Reply by ●September 18, 20152015-09-18
I forgot to add another thought about your "Table 3-16" here:
On Fri, 18 Sep 2015 09:44:06 -0500, you wrote:
>Addressing Mode Length of
>Src Dst No. of Cycles Length of Instruction Example
>Rn &EDE 4 2 MOV R5,&EDE versus
>#N &EDE 5 3 ADD #33,&EDE
as juxtapositioned against the table on page 9-24, section
9.3.1, that I earlier pointed out on SLAA0024. That table I
provided IS explicit. Your table is also explicit. They are
in conflict, it appears. Mine comes from an ancient MSP430
document and it may be wrong, now. I don't know.
So this means to perhaps try out the simulator or, if
possible, to use an actual emulation through a JTAG port and
see what actually transpires.
Can you do that test?
Jon
Posted by: Jon Kirwan
On Fri, 18 Sep 2015 09:44:06 -0500, you wrote:
>Addressing Mode Length of
>Src Dst No. of Cycles Length of Instruction Example
>Rn &EDE 4 2 MOV R5,&EDE versus
>#N &EDE 5 3 ADD #33,&EDE
as juxtapositioned against the table on page 9-24, section
9.3.1, that I earlier pointed out on SLAA0024. That table I
provided IS explicit. Your table is also explicit. They are
in conflict, it appears. Mine comes from an ancient MSP430
document and it may be wrong, now. I don't know.
So this means to perhaps try out the simulator or, if
possible, to use an actual emulation through a JTAG port and
see what actually transpires.
Can you do that test?
Jon
Posted by: Jon Kirwan
Reply by ●September 18, 20152015-09-18
Jon,
I think your argument in using only the figure on page 9-24 of SLAA024 is flawed in that the figure does not account for Constant Generator use for the 6 (from memory?) constants unless the reader makes the conversion to register mode for them. Now we could go back and forth on this for a long time, so I just programmed a second xor.b #0x1,&P1OUT to immediately follow the first. The resulting pulse is 4 cycles long. And, just to be complete I changed the two xors to xor.b #0x11,&P1OUT. This pulse is 5 cycles long.
/end/ message to Jon
So far, I have found two more things:
1) LPM2 needs to be added to the list of LPM 3 and 4 needing 2 extra cycles; Its burst length is the same as LPM3; I have not and probably will not test LPM4.
2)Curiouser and curiouser: If I just comment out the clearing of the low power modes within the ISR, I count a burst of 12 cycles but the 8 cycles for LPM3 Interrupt Acceptance and 5 for RETI says the burst should be 13. (I was about to give a crazy enough analysis here that would have almost been bad enough to justify removing me from the group, but, luckily, I was aroused from my sleep-deprived stupor.)
I'll keep investigating, but may be silent over the weekend and into next week.
Emmett Redd Ph.D. mailto:E...@missouristate.edu
Professor (417)836-5221
Department of Physics, Astronomy, and Materials Science
Missouri State University Fax (417)836-6226
901 SOUTH NATIONAL Lab (417)836-3770
SPRINGFIELD, MO 65897 USA Dept (417)836-5131
In statesmanship get the formalities right, never mind about the moralities. -- Mark Twain.
________________________________________
From: m... [m...]
Sent: Friday, September 18, 2015 12:02 PM
To: MSP430 List
Subject: Re: [msp430] Cycle Counting--Too Many
I forgot to add another thought about your "Table 3-16" here:
On Fri, 18 Sep 2015 09:44:06 -0500, you wrote:
>Addressing Mode Length of
>Src Dst No. of Cycles Length of Instruction Example
>Rn &EDE 4 2 MOV R5,&EDE versus
>#N &EDE 5 3 ADD #33,&EDE
as juxtapositioned against the table on page 9-24, section
9.3.1, that I earlier pointed out on SLAA0024. That table I
provided IS explicit. Your table is also explicit. They are
in conflict, it appears. Mine comes from an ancient MSP430
document and it may be wrong, now. I don't know.
So this means to perhaps try out the simulator or, if
possible, to use an actual emulation through a JTAG port and
see what actually transpires.
Can you do that test?
Jon
Posted by: Jon Kirwan
Posted by: "Redd, Emmett R"
I think your argument in using only the figure on page 9-24 of SLAA024 is flawed in that the figure does not account for Constant Generator use for the 6 (from memory?) constants unless the reader makes the conversion to register mode for them. Now we could go back and forth on this for a long time, so I just programmed a second xor.b #0x1,&P1OUT to immediately follow the first. The resulting pulse is 4 cycles long. And, just to be complete I changed the two xors to xor.b #0x11,&P1OUT. This pulse is 5 cycles long.
/end/ message to Jon
So far, I have found two more things:
1) LPM2 needs to be added to the list of LPM 3 and 4 needing 2 extra cycles; Its burst length is the same as LPM3; I have not and probably will not test LPM4.
2)Curiouser and curiouser: If I just comment out the clearing of the low power modes within the ISR, I count a burst of 12 cycles but the 8 cycles for LPM3 Interrupt Acceptance and 5 for RETI says the burst should be 13. (I was about to give a crazy enough analysis here that would have almost been bad enough to justify removing me from the group, but, luckily, I was aroused from my sleep-deprived stupor.)
I'll keep investigating, but may be silent over the weekend and into next week.
Emmett Redd Ph.D. mailto:E...@missouristate.edu
Professor (417)836-5221
Department of Physics, Astronomy, and Materials Science
Missouri State University Fax (417)836-6226
901 SOUTH NATIONAL Lab (417)836-3770
SPRINGFIELD, MO 65897 USA Dept (417)836-5131
In statesmanship get the formalities right, never mind about the moralities. -- Mark Twain.
________________________________________
From: m... [m...]
Sent: Friday, September 18, 2015 12:02 PM
To: MSP430 List
Subject: Re: [msp430] Cycle Counting--Too Many
I forgot to add another thought about your "Table 3-16" here:
On Fri, 18 Sep 2015 09:44:06 -0500, you wrote:
>Addressing Mode Length of
>Src Dst No. of Cycles Length of Instruction Example
>Rn &EDE 4 2 MOV R5,&EDE versus
>#N &EDE 5 3 ADD #33,&EDE
as juxtapositioned against the table on page 9-24, section
9.3.1, that I earlier pointed out on SLAA0024. That table I
provided IS explicit. Your table is also explicit. They are
in conflict, it appears. Mine comes from an ancient MSP430
document and it may be wrong, now. I don't know.
So this means to perhaps try out the simulator or, if
possible, to use an actual emulation through a JTAG port and
see what actually transpires.
Can you do that test?
Jon
Posted by: Jon Kirwan
Posted by: "Redd, Emmett R"
Reply by ●September 18, 20152015-09-18
On Fri, 18 Sep 2015 14:56:33 -0500, you wrote:
> I think your argument in using only the figure on page 9-24
> of SLAA024 is flawed in that the figure does not account for
> Constant Generator use for the 6 (from memory?) constants
> unless the reader makes the conversion to register mode for
> them.
I completely took your first post's point on this issue, as
well. It makes sense, too. Just as you say. I take your point
above, once again.
> Now we could go back and forth on this for a long
> time,
I really didn't want to belabor things. I just wanted to
tweek your thinking so that you'd do an experiment. The
documentation wasn't outright explicit about it, as I read
through it.
> so I just programmed a second xor.b #0x1,&P1OUT to
> immediately follow the first. The resulting pulse is 4
> cycles long. And, just to be complete I changed the two
> xors to xor.b #0x11,&P1OUT. This pulse is 5 cycles long.
Perfect!
>
> Curiouser and curiouser: If I just comment out the clearing
> of the low power modes within the ISR, I count a burst of 12
> cycles but the 8 cycles for LPM3 Interrupt Acceptance and 5
> for RETI says the burst should be 13.
>
Interesting. I really enjoy seeing the detailed work going on
here and will be very interested in how things resolve as you
work through it. I do similar kinds of tests (often to the
despair of those who would prefer I just accept "handwaving"
and call it "close enough for horseshoes"), so I really like
seeing when someone else is just as anal about the details as
I prefer. Will be watching, so please do update when you have
more information on this.
Jon
Posted by: Jon Kirwan
> I think your argument in using only the figure on page 9-24
> of SLAA024 is flawed in that the figure does not account for
> Constant Generator use for the 6 (from memory?) constants
> unless the reader makes the conversion to register mode for
> them.
I completely took your first post's point on this issue, as
well. It makes sense, too. Just as you say. I take your point
above, once again.
> Now we could go back and forth on this for a long
> time,
I really didn't want to belabor things. I just wanted to
tweek your thinking so that you'd do an experiment. The
documentation wasn't outright explicit about it, as I read
through it.
> so I just programmed a second xor.b #0x1,&P1OUT to
> immediately follow the first. The resulting pulse is 4
> cycles long. And, just to be complete I changed the two
> xors to xor.b #0x11,&P1OUT. This pulse is 5 cycles long.
Perfect!
>
> Curiouser and curiouser: If I just comment out the clearing
> of the low power modes within the ISR, I count a burst of 12
> cycles but the 8 cycles for LPM3 Interrupt Acceptance and 5
> for RETI says the burst should be 13.
>
Interesting. I really enjoy seeing the detailed work going on
here and will be very interested in how things resolve as you
work through it. I do similar kinds of tests (often to the
despair of those who would prefer I just accept "handwaving"
and call it "close enough for horseshoes"), so I really like
seeing when someone else is just as anal about the details as
I prefer. Will be watching, so please do update when you have
more information on this.
Jon
Posted by: Jon Kirwan
Reply by ●September 22, 20152015-09-22
First, a summary and then details will follow.
Emmett Redd Ph.D. mailto:E...@missouristate.edu
Professor (417)836-5221
Department of Physics, Astronomy, and Materials Science
Missouri State University Fax (417)836-6226
901 SOUTH NATIONAL Lab (417)836-3770
SPRINGFIELD, MO 65897 USA Dept (417)836-5131
In statesmanship get the formalities right, never mind about the moralities. -- Mark Twain.
________________________________________
From: m... [m...]
Sent: Friday, September 18, 2015 3:16 PM
To: MSP430 List
Subject: Re: [msp430] Cycle Counting--Too Many
On Fri, 18 Sep 2015 14:56:33 -0500, you wrote:
> I think your argument in using only the figure on page 9-24
> of SLAA024 is flawed in that the figure does not account for
> Constant Generator use for the 6 (from memory?) constants
> unless the reader makes the conversion to register mode for
> them.
I completely took your first post's point on this issue, as
well. It makes sense, too. Just as you say. I take your point
above, once again.
> Now we could go back and forth on this for a long
> time,
I really didn't want to belabor things. I just wanted to
tweek your thinking so that you'd do an experiment. The
documentation wasn't outright explicit about it, as I read
through it.
> so I just programmed a second xor.b #0x1,&P1OUT to
> immediately follow the first. The resulting pulse is 4
> cycles long. And, just to be complete I changed the two
> xors to xor.b #0x11,&P1OUT. This pulse is 5 cycles long.
Perfect!
>
> Curiouser and curiouser: If I just comment out the clearing
> of the low power modes within the ISR, I count a burst of 12
> cycles but the 8 cycles for LPM3 Interrupt Acceptance and 5
> for RETI says the burst should be 13.
>
Interesting. I really enjoy seeing the detailed work going on
here and will be very interested in how things resolve as you
work through it. I do similar kinds of tests (often to the
despair of those who would prefer I just accept "handwaving"
and call it "close enough for horseshoes"), so I really like
seeing when someone else is just as anal about the details as
I prefer. Will be watching, so please do update when you have
more information on this.
Jon
Posted by: Jon Kirwan
Posted by: "Redd, Emmett R"
Emmett Redd Ph.D. mailto:E...@missouristate.edu
Professor (417)836-5221
Department of Physics, Astronomy, and Materials Science
Missouri State University Fax (417)836-6226
901 SOUTH NATIONAL Lab (417)836-3770
SPRINGFIELD, MO 65897 USA Dept (417)836-5131
In statesmanship get the formalities right, never mind about the moralities. -- Mark Twain.
________________________________________
From: m... [m...]
Sent: Friday, September 18, 2015 3:16 PM
To: MSP430 List
Subject: Re: [msp430] Cycle Counting--Too Many
On Fri, 18 Sep 2015 14:56:33 -0500, you wrote:
> I think your argument in using only the figure on page 9-24
> of SLAA024 is flawed in that the figure does not account for
> Constant Generator use for the 6 (from memory?) constants
> unless the reader makes the conversion to register mode for
> them.
I completely took your first post's point on this issue, as
well. It makes sense, too. Just as you say. I take your point
above, once again.
> Now we could go back and forth on this for a long
> time,
I really didn't want to belabor things. I just wanted to
tweek your thinking so that you'd do an experiment. The
documentation wasn't outright explicit about it, as I read
through it.
> so I just programmed a second xor.b #0x1,&P1OUT to
> immediately follow the first. The resulting pulse is 4
> cycles long. And, just to be complete I changed the two
> xors to xor.b #0x11,&P1OUT. This pulse is 5 cycles long.
Perfect!
>
> Curiouser and curiouser: If I just comment out the clearing
> of the low power modes within the ISR, I count a burst of 12
> cycles but the 8 cycles for LPM3 Interrupt Acceptance and 5
> for RETI says the burst should be 13.
>
Interesting. I really enjoy seeing the detailed work going on
here and will be very interested in how things resolve as you
work through it. I do similar kinds of tests (often to the
despair of those who would prefer I just accept "handwaving"
and call it "close enough for horseshoes"), so I really like
seeing when someone else is just as anal about the details as
I prefer. Will be watching, so please do update when you have
more information on this.
Jon
Posted by: Jon Kirwan
Posted by: "Redd, Emmett R"
Reply by ●September 22, 20152015-09-22
Please ignore today's previous email. Windows 10 and my touchpad sent it
before I had put all the information contained in this email.
Update: First a summary and then the details.
Summary: There remain two extra cycles when going into and out of LPM3 and there is still one cycle short when the low-power bits are not cleared and the main never gets to run in active mode.
Details:
Since the xor and oscilloscope functions like a print statement for me in debugging, I decided to put one in between every operation I could. And, since the xor transitions on the falling edge of SMCLK, I will be counting the falling edge as the end of a cpu cycle.
So, with the first instruction in the ISR being an xor, it should be 8 (interrupt acceptance in LPM3) + 4 (xor) = 12 to first LED edge. That is what I count IF the long, SMCLK idling high, cycle is counted as the first cycle. Then comes the bic (5 cycles) to clear the low-power bits and xor (4 cycles) for a total of 9. The next edge comes after the 5-cycle RETI and 4-cycle xor. The next edge comes after a 2-cycle jmp and a 4-cycle xor. Then comes the 2-cycle bis that sets the low-power bits and 2 unexplained cycles before the long cycle counted as the first cycle above.
Speculation: Could it be that it takes an undocumented 2 cycles for the clocks to get into a low power mode like it takes a barely-documented 2 cycles to get out?
When not clearing the low-power bits in the ISR, the SMCLK burst remains 1 cycle short. If RETI is the only instruction, 12 cycles (11 short and 1 long) are all that appear. With the ISR consisting of two xors and RETI, it is 20 cycles long (19 short and 1 long). The first xor indicates that the long cycle remains with the 8 cycles of the interrupt acceptance in LPM3; the RETI is only 4 cycles (not 5 as documented).
I cannot think of any experiments from here.
Emmett Redd Ph.D. mailto:E...@missouristate.edu
Professor (417)836-5221
Department of Physics, Astronomy, and Materials Science
Missouri State University Fax (417)836-6226
901 SOUTH NATIONAL Lab (417)836-3770
SPRINGFIELD, MO 65897 USA Dept (417)836-5131
In statesmanship get the formalities right, never mind about the moralities. -- Mark Twain.
________________________________________
From: m... [m...]
Sent: Friday, September 18, 2015 3:16 PM
To: MSP430 List
Subject: Re: [msp430] Cycle Counting--Too Many
On Fri, 18 Sep 2015 14:56:33 -0500, you wrote:
> I think your argument in using only the figure on page 9-24
> of SLAA024 is flawed in that the figure does not account for
> Constant Generator use for the 6 (from memory?) constants
> unless the reader makes the conversion to register mode for
> them.
I completely took your first post's point on this issue, as
well. It makes sense, too. Just as you say. I take your point
above, once again.
> Now we could go back and forth on this for a long
> time,
I really didn't want to belabor things. I just wanted to
tweek your thinking so that you'd do an experiment. The
documentation wasn't outright explicit about it, as I read
through it.
> so I just programmed a second xor.b #0x1,&P1OUT to
> immediately follow the first. The resulting pulse is 4
> cycles long. And, just to be complete I changed the two
> xors to xor.b #0x11,&P1OUT. This pulse is 5 cycles long.
Perfect!
>
> Curiouser and curiouser: If I just comment out the clearing
> of the low power modes within the ISR, I count a burst of 12
> cycles but the 8 cycles for LPM3 Interrupt Acceptance and 5
> for RETI says the burst should be 13.
>
Interesting. I really enjoy seeing the detailed work going on
here and will be very interested in how things resolve as you
work through it. I do similar kinds of tests (often to the
despair of those who would prefer I just accept "handwaving"
and call it "close enough for horseshoes"), so I really like
seeing when someone else is just as anal about the details as
I prefer. Will be watching, so please do update when you have
more information on this.
Jon
Posted by: Jon Kirwan
Posted by: "Redd, Emmett R"
Update: First a summary and then the details.
Summary: There remain two extra cycles when going into and out of LPM3 and there is still one cycle short when the low-power bits are not cleared and the main never gets to run in active mode.
Details:
Since the xor and oscilloscope functions like a print statement for me in debugging, I decided to put one in between every operation I could. And, since the xor transitions on the falling edge of SMCLK, I will be counting the falling edge as the end of a cpu cycle.
So, with the first instruction in the ISR being an xor, it should be 8 (interrupt acceptance in LPM3) + 4 (xor) = 12 to first LED edge. That is what I count IF the long, SMCLK idling high, cycle is counted as the first cycle. Then comes the bic (5 cycles) to clear the low-power bits and xor (4 cycles) for a total of 9. The next edge comes after the 5-cycle RETI and 4-cycle xor. The next edge comes after a 2-cycle jmp and a 4-cycle xor. Then comes the 2-cycle bis that sets the low-power bits and 2 unexplained cycles before the long cycle counted as the first cycle above.
Speculation: Could it be that it takes an undocumented 2 cycles for the clocks to get into a low power mode like it takes a barely-documented 2 cycles to get out?
When not clearing the low-power bits in the ISR, the SMCLK burst remains 1 cycle short. If RETI is the only instruction, 12 cycles (11 short and 1 long) are all that appear. With the ISR consisting of two xors and RETI, it is 20 cycles long (19 short and 1 long). The first xor indicates that the long cycle remains with the 8 cycles of the interrupt acceptance in LPM3; the RETI is only 4 cycles (not 5 as documented).
I cannot think of any experiments from here.
Emmett Redd Ph.D. mailto:E...@missouristate.edu
Professor (417)836-5221
Department of Physics, Astronomy, and Materials Science
Missouri State University Fax (417)836-6226
901 SOUTH NATIONAL Lab (417)836-3770
SPRINGFIELD, MO 65897 USA Dept (417)836-5131
In statesmanship get the formalities right, never mind about the moralities. -- Mark Twain.
________________________________________
From: m... [m...]
Sent: Friday, September 18, 2015 3:16 PM
To: MSP430 List
Subject: Re: [msp430] Cycle Counting--Too Many
On Fri, 18 Sep 2015 14:56:33 -0500, you wrote:
> I think your argument in using only the figure on page 9-24
> of SLAA024 is flawed in that the figure does not account for
> Constant Generator use for the 6 (from memory?) constants
> unless the reader makes the conversion to register mode for
> them.
I completely took your first post's point on this issue, as
well. It makes sense, too. Just as you say. I take your point
above, once again.
> Now we could go back and forth on this for a long
> time,
I really didn't want to belabor things. I just wanted to
tweek your thinking so that you'd do an experiment. The
documentation wasn't outright explicit about it, as I read
through it.
> so I just programmed a second xor.b #0x1,&P1OUT to
> immediately follow the first. The resulting pulse is 4
> cycles long. And, just to be complete I changed the two
> xors to xor.b #0x11,&P1OUT. This pulse is 5 cycles long.
Perfect!
>
> Curiouser and curiouser: If I just comment out the clearing
> of the low power modes within the ISR, I count a burst of 12
> cycles but the 8 cycles for LPM3 Interrupt Acceptance and 5
> for RETI says the burst should be 13.
>
Interesting. I really enjoy seeing the detailed work going on
here and will be very interested in how things resolve as you
work through it. I do similar kinds of tests (often to the
despair of those who would prefer I just accept "handwaving"
and call it "close enough for horseshoes"), so I really like
seeing when someone else is just as anal about the details as
I prefer. Will be watching, so please do update when you have
more information on this.
Jon
Posted by: Jon Kirwan
Posted by: "Redd, Emmett R"
Reply by ●September 23, 20152015-09-23
Another update: I posted to the Texas Instruments e2e site:
https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/454350 and received
one answer. It contains no direct knowledge nor reference to documentation that
directly applies. Although I don't really mean it to sound negative, it is
a bit of a let-down that the answer may turn out to be the best available.
Emmett Redd Ph.D. mailto:E...@missouristate.edu
Professor (417)836-5221
Department of Physics, Astronomy, and Materials Science
Missouri State University Fax (417)836-6226
901 SOUTH NATIONAL Lab (417)836-3770
SPRINGFIELD, MO 65897 USA Dept (417)836-5131
In statesmanship get the formalities right, never mind about the moralities. -- Mark Twain.
Posted by: "Redd, Emmett R"
Emmett Redd Ph.D. mailto:E...@missouristate.edu
Professor (417)836-5221
Department of Physics, Astronomy, and Materials Science
Missouri State University Fax (417)836-6226
901 SOUTH NATIONAL Lab (417)836-3770
SPRINGFIELD, MO 65897 USA Dept (417)836-5131
In statesmanship get the formalities right, never mind about the moralities. -- Mark Twain.
Posted by: "Redd, Emmett R"
Reply by ●September 23, 20152015-09-23
See that's the problem you have the most notorious virus there is.....
Windows....
On Tue, Sep 22, 2015 at 11:00 AM, 'Redd, Emmett R'
E...@missouristate.edu [msp430] wrote:
> Please ignore today's previous email. Windows 10 and my touchpad sent it
> before I had put all the information contained in this email.
>
> Update: First a summary and then the details.
>
> Summary: There remain two extra cycles when going into and out of LPM3 and
> there is still one cycle short when the low-power bits are not cleared and
> the main never gets to run in active mode.
>
> Details:
>
> Since the xor and oscilloscope functions like a print statement for me in
> debugging, I decided to put one in between every operation I could. And,
> since the xor transitions on the falling edge of SMCLK, I will be counting
> the falling edge as the end of a cpu cycle.
>
> So, with the first instruction in the ISR being an xor, it should be 8
> (interrupt acceptance in LPM3) + 4 (xor) = 12 to first LED edge. That is
> what I count IF the long, SMCLK idling high, cycle is counted as the first
> cycle. Then comes the bic (5 cycles) to clear the low-power bits and xor (4
> cycles) for a total of 9. The next edge comes after the 5-cycle RETI and
> 4-cycle xor. The next edge comes after a 2-cycle jmp and a 4-cycle xor.
> Then comes the 2-cycle bis that sets the low-power bits and 2 unexplained
> cycles before the long cycle counted as the first cycle above.
>
> Speculation: Could it be that it takes an undocumented 2 cycles for the
> clocks to get into a low power mode like it takes a barely-documented 2
> cycles to get out?
>
> When not clearing the low-power bits in the ISR, the SMCLK burst remains 1
> cycle short. If RETI is the only instruction, 12 cycles (11 short and 1
> long) are all that appear. With the ISR consisting of two xors and RETI, it
> is 20 cycles long (19 short and 1 long). The first xor indicates that the
> long cycle remains with the 8 cycles of the interrupt acceptance in LPM3;
> the RETI is only 4 cycles (not 5 as documented).
>
> I cannot think of any experiments from here.
>
> Emmett Redd Ph.D. mailto:E...@missouristate.edu
> Professor (417)836-5221
> Department of Physics, Astronomy, and Materials Science
> Missouri State University Fax (417)836-6226
> 901 SOUTH NATIONAL Lab (417)836-3770
> SPRINGFIELD, MO 65897 USA Dept (417)836-5131
>
> In statesmanship get the formalities right, never mind about the
> moralities. -- Mark Twain.
> ________________________________________
> From: m... [m...]
> Sent: Friday, September 18, 2015 3:16 PM
> To: MSP430 List
> Subject: Re: [msp430] Cycle Counting--Too Many
>
> On Fri, 18 Sep 2015 14:56:33 -0500, you wrote:
>
> > I think your argument in using only the figure on page 9-24
> > of SLAA024 is flawed in that the figure does not account for
> > Constant Generator use for the 6 (from memory?) constants
> > unless the reader makes the conversion to register mode for
> > them.
>
> I completely took your first post's point on this issue, as
> well. It makes sense, too. Just as you say. I take your point
> above, once again.
>
> > Now we could go back and forth on this for a long
> > time,
>
> I really didn't want to belabor things. I just wanted to
> tweek your thinking so that you'd do an experiment. The
> documentation wasn't outright explicit about it, as I read
> through it.
>
> > so I just programmed a second xor.b #0x1,&P1OUT to
> > immediately follow the first. The resulting pulse is 4
> > cycles long. And, just to be complete I changed the two
> > xors to xor.b #0x11,&P1OUT. This pulse is 5 cycles long.
>
> Perfect!
>
> >
> > Curiouser and curiouser: If I just comment out the clearing
> > of the low power modes within the ISR, I count a burst of 12
> > cycles but the 8 cycles for LPM3 Interrupt Acceptance and 5
> > for RETI says the burst should be 13.
> > Interesting. I really enjoy seeing the detailed work going on
> here and will be very interested in how things resolve as you
> work through it. I do similar kinds of tests (often to the
> despair of those who would prefer I just accept "handwaving"
> and call it "close enough for horseshoes"), so I really like
> seeing when someone else is just as anal about the details as
> I prefer. Will be watching, so please do update when you have
> more information on this.
>
> Jon
>
>
> Posted by: Jon Kirwan
>
>
>
>
>
>
--
Thomas J. Grajewski
Windows....
On Tue, Sep 22, 2015 at 11:00 AM, 'Redd, Emmett R'
E...@missouristate.edu [msp430] wrote:
> Please ignore today's previous email. Windows 10 and my touchpad sent it
> before I had put all the information contained in this email.
>
> Update: First a summary and then the details.
>
> Summary: There remain two extra cycles when going into and out of LPM3 and
> there is still one cycle short when the low-power bits are not cleared and
> the main never gets to run in active mode.
>
> Details:
>
> Since the xor and oscilloscope functions like a print statement for me in
> debugging, I decided to put one in between every operation I could. And,
> since the xor transitions on the falling edge of SMCLK, I will be counting
> the falling edge as the end of a cpu cycle.
>
> So, with the first instruction in the ISR being an xor, it should be 8
> (interrupt acceptance in LPM3) + 4 (xor) = 12 to first LED edge. That is
> what I count IF the long, SMCLK idling high, cycle is counted as the first
> cycle. Then comes the bic (5 cycles) to clear the low-power bits and xor (4
> cycles) for a total of 9. The next edge comes after the 5-cycle RETI and
> 4-cycle xor. The next edge comes after a 2-cycle jmp and a 4-cycle xor.
> Then comes the 2-cycle bis that sets the low-power bits and 2 unexplained
> cycles before the long cycle counted as the first cycle above.
>
> Speculation: Could it be that it takes an undocumented 2 cycles for the
> clocks to get into a low power mode like it takes a barely-documented 2
> cycles to get out?
>
> When not clearing the low-power bits in the ISR, the SMCLK burst remains 1
> cycle short. If RETI is the only instruction, 12 cycles (11 short and 1
> long) are all that appear. With the ISR consisting of two xors and RETI, it
> is 20 cycles long (19 short and 1 long). The first xor indicates that the
> long cycle remains with the 8 cycles of the interrupt acceptance in LPM3;
> the RETI is only 4 cycles (not 5 as documented).
>
> I cannot think of any experiments from here.
>
> Emmett Redd Ph.D. mailto:E...@missouristate.edu
> Professor (417)836-5221
> Department of Physics, Astronomy, and Materials Science
> Missouri State University Fax (417)836-6226
> 901 SOUTH NATIONAL Lab (417)836-3770
> SPRINGFIELD, MO 65897 USA Dept (417)836-5131
>
> In statesmanship get the formalities right, never mind about the
> moralities. -- Mark Twain.
> ________________________________________
> From: m... [m...]
> Sent: Friday, September 18, 2015 3:16 PM
> To: MSP430 List
> Subject: Re: [msp430] Cycle Counting--Too Many
>
> On Fri, 18 Sep 2015 14:56:33 -0500, you wrote:
>
> > I think your argument in using only the figure on page 9-24
> > of SLAA024 is flawed in that the figure does not account for
> > Constant Generator use for the 6 (from memory?) constants
> > unless the reader makes the conversion to register mode for
> > them.
>
> I completely took your first post's point on this issue, as
> well. It makes sense, too. Just as you say. I take your point
> above, once again.
>
> > Now we could go back and forth on this for a long
> > time,
>
> I really didn't want to belabor things. I just wanted to
> tweek your thinking so that you'd do an experiment. The
> documentation wasn't outright explicit about it, as I read
> through it.
>
> > so I just programmed a second xor.b #0x1,&P1OUT to
> > immediately follow the first. The resulting pulse is 4
> > cycles long. And, just to be complete I changed the two
> > xors to xor.b #0x11,&P1OUT. This pulse is 5 cycles long.
>
> Perfect!
>
> >
> > Curiouser and curiouser: If I just comment out the clearing
> > of the low power modes within the ISR, I count a burst of 12
> > cycles but the 8 cycles for LPM3 Interrupt Acceptance and 5
> > for RETI says the burst should be 13.
> > Interesting. I really enjoy seeing the detailed work going on
> here and will be very interested in how things resolve as you
> work through it. I do similar kinds of tests (often to the
> despair of those who would prefer I just accept "handwaving"
> and call it "close enough for horseshoes"), so I really like
> seeing when someone else is just as anal about the details as
> I prefer. Will be watching, so please do update when you have
> more information on this.
>
> Jon
>
>
> Posted by: Jon Kirwan
>
>
>
>
>
>
--
Thomas J. Grajewski
Reply by ●September 23, 20152015-09-23
On Wed, 23 Sep 2015 15:48:17 -0500, you wrote:
> Another update: I posted to the Texas Instruments e2e site:
> https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/454350
> and received one answer. It contains no direct knowledge
> nor reference to documentation that directly applies.
> Although I don't really mean it to sound negative, it is a
> bit of a let-down that the answer may turn out to be the
> best available.
Interesting answer you got.
I had been thinking about the pipeline and had prepared
several pages here with it operating the way I see it in my
mind's eye (I've designed a cpu or two in my life, so I have
perhaps a very small clue here.) I didn't publish it here,
though, as I still wanted to find time to go back through it
before showing my ignorance to all and sunder. If I get some
time to complete that work, and feel comfortable about it,
I'll post it here. Meanwhile, I'll save that hand-work for
that moment.
The referenced to the area discussing switching clocks is a
good one. I think you should dwell there a bit and see where
that takes you.
Are you developing classwork/labs?
Jon
Posted by: Jon Kirwan
> Another update: I posted to the Texas Instruments e2e site:
> https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/454350
> and received one answer. It contains no direct knowledge
> nor reference to documentation that directly applies.
> Although I don't really mean it to sound negative, it is a
> bit of a let-down that the answer may turn out to be the
> best available.
Interesting answer you got.
I had been thinking about the pipeline and had prepared
several pages here with it operating the way I see it in my
mind's eye (I've designed a cpu or two in my life, so I have
perhaps a very small clue here.) I didn't publish it here,
though, as I still wanted to find time to go back through it
before showing my ignorance to all and sunder. If I get some
time to complete that work, and feel comfortable about it,
I'll post it here. Meanwhile, I'll save that hand-work for
that moment.
The referenced to the area discussing switching clocks is a
good one. I think you should dwell there a bit and see where
that takes you.
Are you developing classwork/labs?
Jon
Posted by: Jon Kirwan
