Looking at the piece of code provided, I've seen no delay for clock stabilization. Have you provided it? It's important to generate such delay before changing the clock source from DCO to XT2, at least it says so in the MSP430x1xx User's Guide. Probably that 6-MHz frequency on the MCLK comes from the DCO, and not the XT2. Adriano. ----- Original Message ----- From: Sipke de Leeuw <s.de.leeuw@s.de...> To: <msp430@msp4...> Sent: Monday, August 02, 2004 5:46 AM Subject: [msp430] MCLK sourced from XT2 > Hi, > > I have exactly the same problem here. My MSP430F449 MCLK refuses to use the > XT2 clock. Also the SMCLK does use the XT2 clock without problems. I use > this clock for UART and other timers. > > Sipke > > > > -----Oorspronkelijk bericht----- > Van: mspgcc-users-admin@mspg... > [mailto:mspgcc-users-admin@mspg...]Namens Sebastien Taylor > Verzonden: donderdag 22 juli 2004 0:20 > Aan: mspgcc-users@mspg... > Onderwerp: [Mspgcc-users] MCLK sourced from XT2 > > > Hello, I am having a strange problem getting the MCLK to work with an > external 8Mhz XT2. I've set it up along with SMCLK to source from the > XT2, and SMCLK works great at 8Mhz, but the MCLK will only run at 6Mhz. > Does anyone have any ideas? > > _BIS_SR(OSCOFF); /* Disable LFXT1CLK (32Khz) */ > SCFI0 = FN_8; > FLL_CTL1 = SELM_XT2 | SELS; > P1DIR = 0x12; > P1SEL = 0x12; > > > Thanks for any help. > > > > > > > . > > > Yahoo! Groups Links > > > >
Re: MCLK sourced from XT2
Started by ●August 2, 2004
Reply by ●August 2, 20042004-08-02
Adriano,
Here is some C code that works for me:
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
BCSCTL1 &= ~XT2OFF; // Turn on XT2
do {
// Wait for XT2 to stablize
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFFF; i > 0; i--); // Time for flag to set
} while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still
set?
BCSCTL2 |= SELM1+SELS; // Switch to XT2 for MCLK and SMCLK
Richard.
Adriano Pegoraro Caye wrote:
>
> Looking at the piece of code provided, I've seen no delay for clock
> stabilization. Have you provided it? It's important to generate such
delay
> before changing the clock source from DCO to XT2, at least it says so
> in the
> MSP430x1xx User's Guide. Probably that 6-MHz frequency on the MCLK
comes
> from the DCO, and not the XT2.
>
> Adriano.
>
> ----- Original Message -----
> From: Sipke de Leeuw <s.de.leeuw@s.de...>
> To: <msp430@msp4...>
> Sent: Monday, August 02, 2004 5:46 AM
> Subject: [msp430] MCLK sourced from XT2
>
>
> > Hi,
> >
> > I have exactly the same problem here. My MSP430F449 MCLK refuses to
use
> the
> > XT2 clock. Also the SMCLK does use the XT2 clock without problems. I
use
> > this clock for UART and other timers.
> >
> > Sipke
> >
> >
> >
> > -----Oorspronkelijk bericht-----
> > Van: mspgcc-users-admin@mspg...
> > [mailto:mspgcc-users-admin@mspg...]Namens Sebastien Taylor
> > Verzonden: donderdag 22 juli 2004 0:20
> > Aan: mspgcc-users@mspg...
> > Onderwerp: [Mspgcc-users] MCLK sourced from XT2
> >
> >
> > Hello, I am having a strange problem getting the MCLK to work with an
> > external 8Mhz XT2. I've set it up along with SMCLK to source
from the
> > XT2, and SMCLK works great at 8Mhz, but the MCLK will only run at
6Mhz.
> > Does anyone have any ideas?
> >
> > _BIS_SR(OSCOFF); /* Disable LFXT1CLK (32Khz) */
> > SCFI0 = FN_8;
> > FLL_CTL1 = SELM_XT2 | SELS;
> > P1DIR = 0x12;
> > P1SEL = 0x12;
> >
> >
> > Thanks for any help.
> >
> >
> >
> >
> >
> >
> > .
> >
> >
> > >.
>
>
Reply by ●August 2, 20042004-08-02
I took a look in your code, Richard, and I saw no mistakes in it. I really don't know what could be wrong, I just know the details of the '1xx family. Maybe in the '4xx something extra must be done, like initializing the FLL, for example. Adriano. ----- Original Message ----- From: Richard F. Tennis <RTennis@RTen...> To: <msp430@msp4...> Sent: Monday, August 02, 2004 11:35 AM Subject: Re: [msp430] MCLK sourced from XT2 > Adriano, > > Here is some C code that works for me: > > WDTCTL = WDTPW + WDTHOLD; // Stop WDT > > BCSCTL1 &= ~XT2OFF; // Turn on XT2 > do > // Wait for XT2 to stablize > IFG1 &= ~OFIFG; // Clear OSCFault flag > for (i = 0xFFF; i > 0; i--); // Time for flag to set > } while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still > set? > BCSCTL2 |= SELM1+SELS; // Switch to XT2 for MCLK and SMCLK > > Richard. > > Adriano Pegoraro Caye wrote: > > > > > Looking at the piece of code provided, I've seen no delay for clock > > stabilization. Have you provided it? It's important to generate such delay > > before changing the clock source from DCO to XT2, at least it says so > > in the > > MSP430x1xx User's Guide. Probably that 6-MHz frequency on the MCLK comes > > from the DCO, and not the XT2. > > > > Adriano. > > > > ----- Original Message ----- > > From: Sipke de Leeuw <s.de.leeuw@s.de...> > > To: <msp430@msp4...> > > Sent: Monday, August 02, 2004 5:46 AM > > Subject: [msp430] MCLK sourced from XT2 > > > > > > > Hi, > > > > > > I have exactly the same problem here. My MSP430F449 MCLK refuses to use > > the > > > XT2 clock. Also the SMCLK does use the XT2 clock without problems. I use > > > this clock for UART and other timers. > > > > > > Sipke > > > > > > > > > > > > -----Oorspronkelijk bericht----- > > > Van: mspgcc-users-admin@mspg... > > > [mailto:mspgcc-users-admin@mspg...]Namens Sebastien Taylor > > > Verzonden: donderdag 22 juli 2004 0:20 > > > Aan: mspgcc-users@mspg... > > > Onderwerp: [Mspgcc-users] MCLK sourced from XT2 > > > > > > > > > Hello, I am having a strange problem getting the MCLK to work with an > > > external 8Mhz XT2. I've set it up along with SMCLK to source from the > > > XT2, and SMCLK works great at 8Mhz, but the MCLK will only run at 6Mhz. > > > Does anyone have any ideas? > > > > > > _BIS_SR(OSCOFF); /* Disable LFXT1CLK (32Khz) */ > > > SCFI0 = FN_8; > > > FLL_CTL1 = SELM_XT2 | SELS; > > > P1DIR = 0x12; > > > P1SEL = 0x12; > > > > > > > > > Thanks for any help. > > > > > > > > > > > > > > > > > > > > > . > > > > > > > > > >. > > > > > > > > > > > > > > . > > > Yahoo! Groups Links > > > >
Reply by ●August 3, 20042004-08-03
I am using the MSP430-449STK2 board (msp430f449) from Olimex. This board
contains an 32768 Hz crystal for the XT1 oscillator and an 8 MHz crystal for
the XT2 oscillator.
FLL_CTL0 and FLL_CTL1 are both initialized with 0x00. (XT2=ON) After that I
wait
until the XT2OF bit is cleared. When the 8MHz crystal is running I switch
the SMCLK and the MCLK so they use the XT2 clock. After this switch, SMCLK
is indeed 8MHz (checked by using this clock for timer) but MCLK seems to run
at the DCO frequency because I don't see any improvement in processing
speed.
-----Oorspronkelijk bericht-----
Van: Richard F. Tennis [mailto:RTennis@RTen...]
Verzonden: maandag 2 augustus 2004 16:36
Aan: msp430@msp4...
Onderwerp: Re: [msp430] MCLK sourced from XT2
Adriano,
Here is some C code that works for me:
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
BCSCTL1 &= ~XT2OFF; // Turn on XT2
do {
// Wait for XT2 to stablize
IFG1 &= ~OFIFG; // Clear OSCFault flag
for (i = 0xFFF; i > 0; i--); // Time for flag to set
} while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still
set?
BCSCTL2 |= SELM1+SELS; // Switch to XT2 for MCLK and SMCLK
Richard.
Adriano Pegoraro Caye wrote:
>
> Looking at the piece of code provided, I've seen no delay for clock
> stabilization. Have you provided it? It's important to generate such
delay
> before changing the clock source from DCO to XT2, at least it says so
> in the
> MSP430x1xx User's Guide. Probably that 6-MHz frequency on the MCLK
comes
> from the DCO, and not the XT2.
>
> Adriano.
>
> ----- Original Message -----
> From: Sipke de Leeuw <s.de.leeuw@s.de...>
> To: <msp430@msp4...>
> Sent: Monday, August 02, 2004 5:46 AM
> Subject: [msp430] MCLK sourced from XT2
>
>
> > Hi,
> >
> > I have exactly the same problem here. My MSP430F449 MCLK refuses to
use
> the
> > XT2 clock. Also the SMCLK does use the XT2 clock without problems. I
use
> > this clock for UART and other timers.
> >
> > Sipke
> >
> >
> >
> > -----Oorspronkelijk bericht-----
> > Van: mspgcc-users-admin@mspg...
> > [mailto:mspgcc-users-admin@mspg...]Namens Sebastien Taylor
> > Verzonden: donderdag 22 juli 2004 0:20
> > Aan: mspgcc-users@mspg...
> > Onderwerp: [Mspgcc-users] MCLK sourced from XT2
> >
> >
> > Hello, I am having a strange problem getting the MCLK to work with an
> > external 8Mhz XT2. I've set it up along with SMCLK to source
from the
> > XT2, and SMCLK works great at 8Mhz, but the MCLK will only run at
6Mhz.
> > Does anyone have any ideas?
> >
> > _BIS_SR(OSCOFF); /* Disable LFXT1CLK (32Khz) */
> > SCFI0 = FN_8;
> > FLL_CTL1 = SELM_XT2 | SELS;
> > P1DIR = 0x12;
> > P1SEL = 0x12;
> >
> >
> > Thanks for any help.
> >
> >
> >
> >
> >
> >
> > .
> >
> >
> > >.
>
>
.
Yahoo! Groups Links
Reply by ●August 3, 20042004-08-03
Have you tried to configure an I/O pin as the MCLK output? By doing this, you can see with an oscilloscope what is the exact frequency MCLK is running. See the "Terminal Functions" list in the datasheet of the MSP you're using to find out what I/O pin have this capacity. Adriano. ----- Original Message ----- From: Sipke de Leeuw <s.de.leeuw@s.de...> To: <msp430@msp4...> Sent: Tuesday, August 03, 2004 3:59 AM Subject: RE: [msp430] MCLK sourced from XT2 > > I am using the MSP430-449STK2 board (msp430f449) from Olimex. This board > contains an 32768 Hz crystal for the XT1 oscillator and an 8 MHz crystal for > the XT2 oscillator. > FLL_CTL0 and FLL_CTL1 are both initialized with 0x00. (XT2=ON) After that I > wait > until the XT2OF bit is cleared. When the 8MHz crystal is running I switch > the SMCLK and the MCLK so they use the XT2 clock. After this switch, SMCLK > is indeed 8MHz (checked by using this clock for timer) but MCLK seems to run > at the DCO frequency because I don't see any improvement in processing > speed. > > -----Oorspronkelijk bericht----- > Van: Richard F. Tennis [mailto:RTennis@RTen...] > Verzonden: maandag 2 augustus 2004 16:36 > Aan: msp430@msp4... > Onderwerp: Re: [msp430] MCLK sourced from XT2 > > > Adriano, > > Here is some C code that works for me: > > WDTCTL = WDTPW + WDTHOLD; // Stop WDT > > BCSCTL1 &= ~XT2OFF; // Turn on XT2 > do { > // Wait for XT2 to stablize > IFG1 &= ~OFIFG; // Clear OSCFault flag > for (i = 0xFFF; i > 0; i--); // Time for flag to set > } while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still > set? > BCSCTL2 |= SELM1+SELS; // Switch to XT2 for MCLK and SMCLK > > Richard. > > Adriano Pegoraro Caye wrote: > > > > > Looking at the piece of code provided, I've seen no delay for clock > > stabilization. Have you provided it? It's important to generate such delay > > before changing the clock source from DCO to XT2, at least it says so > > in the > > MSP430x1xx User's Guide. Probably that 6-MHz frequency on the MCLK comes > > from the DCO, and not the XT2. > > > > Adriano. > > > > ----- Original Message ----- > > From: Sipke de Leeuw <s.de.leeuw@s.de...> > > To: <msp430@msp4...> > > Sent: Monday, August 02, 2004 5:46 AM > > Subject: [msp430] MCLK sourced from XT2 > > > > > > > Hi, > > > > > > I have exactly the same problem here. My MSP430F449 MCLK refuses to use > > the > > > XT2 clock. Also the SMCLK does use the XT2 clock without problems. I use > > > this clock for UART and other timers. > > > > > > Sipke > > > > > > > > > > > > -----Oorspronkelijk bericht----- > > > Van: mspgcc-users-admin@mspg... > > > [mailto:mspgcc-users-admin@mspg...]Namens Sebastien Taylor > > > Verzonden: donderdag 22 juli 2004 0:20 > > > Aan: mspgcc-users@mspg... > > > Onderwerp: [Mspgcc-users] MCLK sourced from XT2 > > > > > > > > > Hello, I am having a strange problem getting the MCLK to work with an > > > external 8Mhz XT2. I've set it up along with SMCLK to source from the > > > XT2, and SMCLK works great at 8Mhz, but the MCLK will only run at 6Mhz. > > > Does anyone have any ideas? > > > > > > _BIS_SR(OSCOFF); /* Disable LFXT1CLK (32Khz) */ > > > SCFI0 = FN_8; > > > FLL_CTL1 = SELM_XT2 | SELS; > > > P1DIR = 0x12; > > > P1SEL = 0x12; > > > > > > > > > Thanks for any help. > > >
Reply by ●August 3, 20042004-08-03
Allowing the clock to stabilise isn't simply a case of waiting. There
is
a procedure outlined by Ti, and posted here in various formats on
several occasions. Failure to follow this will result in symptoms
similar to those you describe, although your assesment of MCLK is
subjective, you cannot accurately judge this without measuring MCLK. If
you can't output it on a pin disable all interrupts and run a short loop
on any out put pin:-
loop:
xor.b #bit0,&portn
jmp loop
This is a 12 clock cycle waveform
Al
Sipke de Leeuw wrote:
> I am using the MSP430-449STK2 board (msp430f449) from Olimex. This board
> contains an 32768 Hz crystal for the XT1 oscillator and an 8 MHz crystal
for
> the XT2 oscillator.
> FLL_CTL0 and FLL_CTL1 are both initialized with 0x00. (XT2=ON) After that I
> wait
> until the XT2OF bit is cleared. When the 8MHz crystal is running I switch
> the SMCLK and the MCLK so they use the XT2 clock. After this switch, SMCLK
> is indeed 8MHz (checked by using this clock for timer) but MCLK seems to
run
> at the DCO frequency because I don't see any improvement in processing
> speed.
>
> -----Oorspronkelijk bericht-----
> Van: Richard F. Tennis [mailto:RTennis@RTen...]
> Verzonden: maandag 2 augustus 2004 16:36
> Aan: msp430@msp4...
> Onderwerp: Re: [msp430] MCLK sourced from XT2
>
>
> Adriano,
>
> Here is some C code that works for me:
>
> WDTCTL = WDTPW + WDTHOLD; // Stop WDT
>
> BCSCTL1 &= ~XT2OFF; // Turn on XT2
> do {
> // Wait for XT2 to stablize
> IFG1 &= ~OFIFG; // Clear OSCFault flag
> for (i = 0xFFF; i > 0; i--); // Time for flag to set
> } while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still
> set?
> BCSCTL2 |= SELM1+SELS; // Switch to XT2 for MCLK and
SMCLK
>
> Richard.
>
> Adriano Pegoraro Caye wrote:
>
>
>>Looking at the piece of code provided, I've seen no delay for clock
>>stabilization. Have you provided it? It's important to generate
such delay
>>before changing the clock source from DCO to XT2, at least it says so
>>in the
>>MSP430x1xx User's Guide. Probably that 6-MHz frequency on the MCLK
comes
>>from the DCO, and not the XT2.
>>
>>Adriano.
>>
>>----- Original Message -----
>>From: Sipke de Leeuw <s.de.leeuw@s.de...>
>>To: <msp430@msp4...>
>>Sent: Monday, August 02, 2004 5:46 AM
>>Subject: [msp430] MCLK sourced from XT2
>>
>>
>>
>>>Hi,
>>>
>>>I have exactly the same problem here. My MSP430F449 MCLK refuses to
use
>>
>>the
>>
>>>XT2 clock. Also the SMCLK does use the XT2 clock without problems. I
use
>>>this clock for UART and other timers.
>>>
>>>Sipke
>>>
>>>
>>>
>>>-----Oorspronkelijk bericht-----
>>>Van: mspgcc-users-admin@mspg...
>>>[mailto:mspgcc-users-admin@mspg...]Namens Sebastien Taylor
>>>Verzonden: donderdag 22 juli 2004 0:20
>>>Aan: mspgcc-users@mspg...
>>>Onderwerp: [Mspgcc-users] MCLK sourced from XT2
>>>
>>>
>>>Hello, I am having a strange problem getting the MCLK to work with
an
>>>external 8Mhz XT2. I've set it up along with SMCLK to source
from the
>>>XT2, and SMCLK works great at 8Mhz, but the MCLK will only run at
6Mhz.
>>> Does anyone have any ideas?
>>>
>>>_BIS_SR(OSCOFF); /* Disable LFXT1CLK (32Khz) */
>>>SCFI0 = FN_8;
>>>FLL_CTL1 = SELM_XT2 | SELS;
>>>P1DIR = 0x12;
>>>P1SEL = 0x12;
>>>
>>>
>>>Thanks for any help.
>>>
>>>
>>>
>>>
>>>
>>>
>>>.
>>>
>>>
>>>>.
>>
>>
>
>
>
>
>
>
>
>
>
>
> .
>
>
> Yahoo! Groups Links
>
>
>
>
>
>
>
>
>
>
> .
>
>
> Yahoo! Groups Links
>
>
>
>
>
>
Reply by ●August 4, 20042004-08-04
Hi Al,
Thanks for your info. I use the following piece of code to 'wait' for
the
oscillator to become stable. I also used other than the F449 so I know the
procedure to wait is a little different.
while ( FLL_CTL0 & XT2OF )
{
/* --
* The XT2OF will be reset automatically
* when there is no more fault condition.
*/
for ( delay = 0; delay < 1000; delay += 1 )
{
/* ---
* Hmmmm ... just waste some time here ...
*/;
}
}
Sipke
-----Oorspronkelijk bericht-----
Van: onestone [mailto:onestone@ones...]
Verzonden: dinsdag 3 augustus 2004 18:13
Aan: msp430@msp4...
Onderwerp: Re: [msp430] MCLK sourced from XT2
Allowing the clock to stabilise isn't simply a case of waiting. There is
a procedure outlined by Ti, and posted here in various formats on
several occasions. Failure to follow this will result in symptoms
similar to those you describe, although your assesment of MCLK is
subjective, you cannot accurately judge this without measuring MCLK. If
you can't output it on a pin disable all interrupts and run a short loop
on any out put pin:-
loop:
xor.b #bit0,&portn
jmp loop
This is a 12 clock cycle waveform
Al
Sipke de Leeuw wrote:
> I am using the MSP430-449STK2 board (msp430f449) from Olimex. This board
> contains an 32768 Hz crystal for the XT1 oscillator and an 8 MHz crystal
for
> the XT2 oscillator.
> FLL_CTL0 and FLL_CTL1 are both initialized with 0x00. (XT2=ON) After that
I
> wait
> until the XT2OF bit is cleared. When the 8MHz crystal is running I switch
> the SMCLK and the MCLK so they use the XT2 clock. After this switch, SMCLK
> is indeed 8MHz (checked by using this clock for timer) but MCLK seems to
run
> at the DCO frequency because I don't see any
improvement in processing
> speed.
>
> -----Oorspronkelijk bericht-----
> Van: Richard F. Tennis [mailto:RTennis@RTen...]
> Verzonden: maandag 2 augustus 2004 16:36
> Aan: msp430@msp4...
> Onderwerp: Re: [msp430] MCLK sourced from XT2
>
>
> Adriano,
>
> Here is some C code that works for me:
>
> WDTCTL = WDTPW + WDTHOLD; // Stop WDT
>
> BCSCTL1 &= ~XT2OFF; // Turn on XT2
> do {
> // Wait for XT2 to stablize
> IFG1 &= ~OFIFG; // Clear OSCFault flag
> for (i = 0xFFF; i > 0; i--); // Time for flag to set
> } while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still
> set?
> BCSCTL2 |= SELM1+SELS; // Switch to XT2 for MCLK and
SMCLK
>
> Richard.
>
> Adriano Pegoraro Caye wrote:
>
>
>>Looking at the piece of code provided, I've seen no delay for clock
>>stabilization. Have you provided it? It's important to generate
such delay
>>before changing the clock source from DCO to XT2, at least it says so
>>in the
>>MSP430x1xx User's Guide. Probably that 6-MHz frequency on the MCLK
comes
>>from the DCO, and not the XT2.
>>
>>Adriano.
>>
>>----- Original Message -----
>>From: Sipke de Leeuw <s.de.leeuw@s.de...>
>>To: <msp430@msp4...>
>>Sent: Monday, August 02, 2004 5:46 AM
>>Subject: [msp430] MCLK sourced from XT2
>>
>>
>>
>>>Hi,
>>>
>>>I have exactly the same problem here. My MSP430F449 MCLK refuses to
use
>>
>>the
>>
>>>XT2 clock. Also the SMCLK does use the XT2 clock without problems. I
use
>>>this clock for UART and other timers.
>>>
>>>Sipke
>>>
>>>
>>>
>>>-----Oorspronkelijk bericht-----
>>>Van: mspgcc-users-admin@mspg...
>>>[mailto:mspgcc-users-admin@mspg...]Namens Sebastien Taylor
>>>Verzonden: donderdag 22 juli 2004 0:20
>>>Aan: mspgcc-users@mspg...
>>>Onderwerp: [Mspgcc-users] MCLK sourced from XT2
>>>
>>>
>>>Hello, I am having a strange problem getting the MCLK to work with
an
>>>external 8Mhz XT2. I've set it up along with SMCLK to source
from the
>>>XT2, and SMCLK works great at 8Mhz, but the MCLK will only run at
6Mhz.
>>> Does anyone have any ideas?
>>>
>>>_BIS_SR(OSCOFF); /* Disable LFXT1CLK (32Khz) */
>>>SCFI0 = FN_8;
>>>FLL_CTL1 = SELM_XT2 | SELS;
>>>P1DIR = 0x12;
>>>P1SEL = 0x12;
>>>
>>>
>>>Thanks for any help.
>>>
>>>
>>>
>>>
>>>
>>>
>>>.
>>>
>>>
>>>>.
>>
>>
>
>
>
>
>
>
>
>
>
>
> .
>
>
> Yahoo! Groups Links
>
>
>
>
>
>
>
>
>
>
> .
>
>
> Yahoo! Groups Links
>
>
>
>
>
>
.
Yahoo! Groups Links
Reply by ●August 4, 20042004-08-04
Sipke, as far as I read the '449 user guide, you still need to recheck
the flag, as in the '149. I would try the '149 style start up just in
case.
Al
Sipke de Leeuw wrote:
> Hi Al,
>
> Thanks for your info. I use the following piece of code to 'wait'
for the
> oscillator to become stable. I also used other than the F449 so I know the
> procedure to wait is a little different.
>
> while ( FLL_CTL0 & XT2OF )
> {
> /* --
> * The XT2OF will be reset automatically
> * when there is no more fault condition.
> */
>
> for ( delay = 0; delay < 1000; delay += 1 )
> {
> /* ---
> * Hmmmm ... just waste some time here ...
> */;
> }
> }
>
>
>
> Sipke
>
>
>
> -----Oorspronkelijk bericht-----
> Van: onestone [mailto:onestone@ones...]
> Verzonden: dinsdag 3 augustus 2004 18:13
> Aan: msp430@msp4...
> Onderwerp: Re: [msp430] MCLK sourced from XT2
>
>
> Allowing the clock to stabilise isn't simply a case of waiting. There
is
> a procedure outlined by Ti, and posted here in various formats on
> several occasions. Failure to follow this will result in symptoms
> similar to those you describe, although your assesment of MCLK is
> subjective, you cannot accurately judge this without measuring MCLK. If
> you can't output it on a pin disable all interrupts and run a short
loop
> on any out put pin:-
>
> loop:
> xor.b #bit0,&portn
> jmp loop
>
> This is a 12 clock cycle waveform
>
> Al
>
> Sipke de Leeuw wrote:
>
>>I am using the MSP430-449STK2 board (msp430f449) from Olimex. This board
>>contains an 32768 Hz crystal for the XT1 oscillator and an 8 MHz crystal
>
> for
>
>>the XT2 oscillator.
>>FLL_CTL0 and FLL_CTL1 are both initialized with 0x00. (XT2=ON) After
that
>
> I
>
>>wait
>>until the XT2OF bit is cleared. When the 8MHz crystal is running I
switch
>>the SMCLK and the MCLK so they use the XT2 clock. After this switch,
SMCLK
>>is indeed 8MHz (checked by using this clock for timer) but MCLK seems to
>
> run
>
>>at the DCO frequency because I don't see any improvement in
processing
>>speed.
>>
>>-----Oorspronkelijk bericht-----
>>Van: Richard F. Tennis [mailto:RTennis@RTen...]
>>Verzonden: maandag 2 augustus 2004 16:36
>>Aan: msp430@msp4...
>>Onderwerp: Re: [msp430] MCLK sourced from XT2
>>
>>
>>Adriano,
>>
>>Here is some C code that works for me:
>>
>> WDTCTL = WDTPW + WDTHOLD; // Stop WDT
>>
>> BCSCTL1 &= ~XT2OFF; // Turn on XT2
>> do {
>>// Wait for XT2 to stablize
>> IFG1 &= ~OFIFG; // Clear OSCFault flag
>> for (i = 0xFFF; i > 0; i--); // Time for flag to set
>> } while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still
>>set?
>> BCSCTL2 |= SELM1+SELS; // Switch to XT2 for MCLK
and
>
> SMCLK
>
>>Richard.
>>
>>Adriano Pegoraro Caye wrote:
>>
>>
>>
>>>Looking at the piece of code provided, I've seen no delay for
clock
>>>stabilization. Have you provided it? It's important to generate
such delay
>>>before changing the clock source from DCO to XT2, at least it says
so
>>>in the
>>>MSP430x1xx User's Guide. Probably that 6-MHz frequency on the
MCLK comes
>>
>>>from the DCO, and not the XT2.
>>
>>>Adriano.
>>>
>>>----- Original Message -----
>>>From: Sipke de Leeuw <s.de.leeuw@s.de...>
>>>To: <msp430@msp4...>
>>>Sent: Monday, August 02, 2004 5:46 AM
>>>Subject: [msp430] MCLK sourced from XT2
>>>
>>>
>>>
>>>
>>>>Hi,
>>>>
>>>>I have exactly the same problem here. My MSP430F449 MCLK refuses
to use
>>>
>>>the
>>>
>>>
>>>>XT2 clock. Also the SMCLK does use the XT2 clock without
problems. I use
>>>>this clock for UART and other timers.
>>>>
>>>>Sipke
>>>>
>>>>
>>>>
>>>>-----Oorspronkelijk bericht-----
>>>>Van: mspgcc-users-admin@mspg...
>>>>[mailto:mspgcc-users-admin@mspg...]Namens Sebastien Taylor
>>>>Verzonden: donderdag 22 juli 2004 0:20
>>>>Aan: mspgcc-users@mspg...
>>>>Onderwerp: [Mspgcc-users] MCLK sourced from XT2
>>>>
>>>>
>>>>Hello, I am having a strange problem getting the MCLK to work
with an
>>>>external 8Mhz XT2. I've set it up along with SMCLK to
source from the
>>>>XT2, and SMCLK works great at 8Mhz, but the MCLK will only run
at 6Mhz.
>>>> Does anyone have any ideas?
>>>>
>>>>_BIS_SR(OSCOFF); /* Disable LFXT1CLK (32Khz) */
>>>>SCFI0 = FN_8;
>>>>FLL_CTL1 = SELM_XT2 | SELS;
>>>>P1DIR = 0x12;
>>>>P1SEL = 0x12;
>>>>
>>>>
>>>>Thanks for any help.
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>.
>>>>
>>>>
>>>>>.
>>>
>>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>.
>>
>>
>>Yahoo! Groups Links
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>.
>>
>>
>>Yahoo! Groups Links
>>
>>
>>
>>
>>
>>
>
>
>
>
>
> .
>
>
> Yahoo! Groups Links
>
>
>
>
>
>
>
>
>
>
> .
>
>
> Yahoo! Groups Links
>
>
>
>
>
>
Reply by ●August 4, 20042004-08-04
Hi Al, I recheck the flag every while loop until the flag is cleared. This flag is a read-only flag of the FLL_CTL0 register so resetting the flag in software cannot be done. I am almost sure this routines works as it should. In a testversion of the software I count the number of times the while loop loops, and the counter stops at 2 or 3 ... So I am pretty sure the clock has stabelized before I try to switch the MCLK to it. However it doesn't seem te work. Sipke -----Oorspronkelijk bericht----- Van: onestone [mailto:onestone@ones...] Verzonden: woensdag 4 augustus 2004 12:08 Aan: msp430@msp4... Onderwerp: Re: [msp430] MCLK sourced from XT2 Sipke, as far as I read the '449 user guide, you still need to recheck the flag, as in the '149. I would try the '149 style start up just in case. Al Sipke de Leeuw wrote: > Hi Al, > > Thanks for your info. I use the following piece of code to 'wait' for the > oscillator to become stable. I also used other than the F449 so I know the > procedure to wait is a little different. > > while ( FLL_CTL0 & XT2OF ) > { > /* -- > * The XT2OF will be reset automatically > * when there is no more fault condition. > */ > > for ( delay = 0; delay < 1000; delay += 1 ) > { > /* --- > * Hmmmm ... just waste some time here ... > */; > } > } > > > > Sipke > > > > -----Oorspronkelijk bericht----- > Van: onestone [mailto:onestone@ones...] > Verzonden: dinsdag 3 augustus 2004 18:13 > Aan: msp430@msp4... > Onderwerp: Re: [msp430] MCLK sourced from XT2 > > > Allowing the clock to stabilise isn't simply a case of waiting. There is > a procedure outlined by Ti, and posted here in various formats on > several occasions. Failure to follow this will result in symptoms > similar to those you describe, although your assesment of MCLK is > subjective, you cannot accurately judge this without measuring MCLK. If > you can't output it on a pin disable all interrupts and run a short loop > on any out put pin:- > > loop: > xor.b #bit0,&portn > jmp loop > > This is a 12 clock cycle waveform > > Al > > Sipke de Leeuw wrote: > >>I am using the MSP430-449STK2 board (msp430f449) from Olimex. This board >>contains an 32768 Hz crystal for the XT1 oscillator and an 8 MHz crystal > > for > >>the XT2 oscillator. >>FLL_CTL0 and FLL_CTL1 are both initialized with 0x00. (XT2=ON) After that > > I > >>wait >>until the XT2OF bit is cleared. When the 8MHz crystal is running I switch >>the SMCLK and the MCLK so they use the XT2 clock. After this switch, SMCLK >>is indeed 8MHz (checked by using this clock for timer) but MCLK seems to > > run > >>at the DCO frequency because I don't see any improvement in processing >>speed. >> >>-----Oorspronkelijk bericht----- >>Van: Richard F. Tennis [mailto:RTennis@RTen...] >>Verzonden: maandag 2 augustus 2004 16:36 >>Aan: msp430@msp4... >>Onderwerp: Re: [msp430] MCLK sourced from XT2 >> >> >>Adriano, >> >>Here is some C code that works for me: >> >> WDTCTL = WDTPW + WDTHOLD; // Stop WDT >> >> BCSCTL1 &= ~XT2OFF; // Turn on XT2 >> do { >>// Wait for XT2 to stablize >> IFG1 &= ~OFIFG; // Clear OSCFault flag >> for (i = 0xFFF; i > 0; i--); // Time for flag to set >> } while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still >>set? >> BCSCTL2 |= SELM1+SELS; // Switch to XT2 for MCLK and > > SMCLK > >>Richard. >> >>Adriano Pegoraro Caye wrote: >> >> >> >>>Looking at the piece of code provided, I've seen no delay for clock >>>stabilization. Have you provided it? It's important to generate such delay >>>before changing the clock source from DCO to XT2, at least it says so >>>in the >>>MSP430x1xx User's Guide. Probably that 6-MHz frequency on the MCLK comes >> >>>from the DCO, and not the XT2. >> >>>Adriano. >>> >>>----- Original Message ----- >>>From: Sipke de Leeuw <s.de.leeuw@s.de...> >>>To: <msp430@msp4...> >>>Sent: Monday, August 02, 2004 5:46 AM >>>Subject: [msp430] MCLK sourced from XT2 >>> >>> >>> >>> >>>>Hi, >>>> >>>>I have exactly the same problem here. My MSP430F449 MCLK refuses to use >>> >>>the >>> >>> >>>>XT2 clock. Also the SMCLK does use the XT2 clock without problems. I use >>>>this clock for UART and other timers. >>>> >>>>Sipke >>>> >>>> >>>> >>>>-----Oorspronkelijk bericht----- >>>>Van: mspgcc-users-admin@mspg... >>>>[mailto:mspgcc-users-admin@mspg...]Namens Sebastien Taylor >>>>Verzonden: donderdag 22 juli 2004 0:20 >>>>Aan: mspgcc-users@mspg... >>>>Onderwerp: [Mspgcc-users] MCLK sourced from XT2 >>>> >>>> >>>>Hello, I am having a strange problem getting the MCLK to work with an >>>>external 8Mhz XT2. I've set it up along with SMCLK to source from the >>>>XT2, and SMCLK works great at 8Mhz, but the MCLK will only run at 6Mhz. >>>> Does anyone have any ideas? >>>> >>>>_BIS_SR(OSCOFF); /* Disable LFXT1CLK (32Khz) */ >>>>SCFI0 = FN_8; >>>>FLL_CTL1 = SELM_XT2 | SELS; >>>>P1DIR = 0x12; >>>>P1SEL = 0x12; >>>> >>>> >>>>Thanks for any help. >>>> >>>> >>>> >>>> >>>> >>>> >>>>. >>>> >>>> >>>>>. >>> >>> >> >> >> >> >> >> >> >> >> >> >>. >> >> >>Yahoo! Groups Links >> >> >> >> >> >> >> >> >> >> >>. >> >> >>Yahoo! Groups Links >> >> >> >> >> >> > > > > > > . > > > Yahoo! Groups Links > > > > > > > > > > > . > > > Yahoo! Groups Links > > > > > > . Yahoo! Groups Links
Reply by ●August 4, 20042004-08-04
Sipke
Here is the code I've been using for quite a while.
Regards
-Bill Knight
R O SoftWare
register int delay;
...
// wait for (LF)XT1 oscillator to come up
// clear OSC fault flag & set delay count
// exit loop when no fault for delay count
for (IFG1 &= ~OFIFG, delay = 255; delay; /* nothing */ )
{
if (IFG1 & OFIFG) // check OSC fault flag
{
// it's set
IFG1 &= ~OFIFG; // clear OSC fault flag
delay = 255; // reset delay count
}
else
--delay; // clear, decrement delay
}
On Wed, 4 Aug 2004 13:13:46 +0200, Sipke de Leeuw wrote:
>Hi Al,
>I recheck the flag every while loop until the flag
is cleared. This flag is
>a read-only flag of the FLL_CTL0 register so resetting the flag in software
>cannot be done.
>I am almost sure this routines works as it should. In a testversion of the
>software I count the number of times the while loop loops, and the counter
>stops at 2 or 3 ...
>So I am pretty sure the clock has stabelized before I try to switch the MCLK
>to it. However it doesn't seem te work.
>Sipke
>-----Oorspronkelijk bericht-----
>Van: onestone [mailto:onestone@ones...]
>Verzonden: woensdag 4 augustus 2004 12:08
>Aan: msp430@msp4...
>Onderwerp: Re: [msp430] MCLK sourced from XT2
>Sipke, as far as I read the '449 user guide,
you still need to recheck
>the flag, as in the '149. I would try the '149 style start up just
in case.
>Al
>Sipke de Leeuw wrote:
>> Hi Al,
>>
>> Thanks for your info. I use the following piece of code to
'wait' for the
>> oscillator to become stable. I also used other than the F449 so I know
the
>> procedure to wait is a little different.
>>
>> while ( FLL_CTL0 & XT2OF )
>> {
>> /* --
>> * The XT2OF will be reset automatically
>> * when there is no more fault condition.
>> */
>>
>> for ( delay = 0; delay < 1000; delay += 1 )
>> {
>> /* ---
>> * Hmmmm ... just waste some time here ...
>> */;
>> }
>> }
>>
>>
>>
>> Sipke
>>
>>
>>
>> -----Oorspronkelijk bericht-----
>> Van: onestone [mailto:onestone@ones...]
>> Verzonden: dinsdag 3 augustus 2004 18:13
>> Aan: msp430@msp4...
>> Onderwerp: Re: [msp430] MCLK sourced from XT2
>>
>>
>> Allowing the clock to stabilise isn't simply a case of waiting.
There is
>> a procedure outlined by Ti, and posted here in various formats on
>> several occasions. Failure to follow this will result in symptoms
>> similar to those you describe, although your assesment of MCLK is
>> subjective, you cannot accurately judge this without measuring MCLK. If
>> you can't output it on a pin disable all interrupts and run a
short loop
>> on any out put pin:-
>>
>> loop:
>> xor.b #bit0,&portn
>> jmp loop
>>
>> This is a 12 clock cycle waveform
>>
>> Al
>>
>> Sipke de Leeuw wrote:
>>
>>>I am using the MSP430-449STK2 board (msp430f449) from Olimex. This
board
>>>contains an 32768 Hz crystal for the XT1 oscillator and an 8 MHz
crystal
>>
>> for
>>
>>>the XT2 oscillator.
>>>FLL_CTL0 and FLL_CTL1 are both initialized with 0x00. (XT2=ON) After
that
>>
>> I
>>
>>>wait
>>>until the XT2OF bit is cleared. When the 8MHz crystal is running I
switch
>>>the SMCLK and the MCLK so they use the XT2 clock. After this switch,
SMCLK
>>>is indeed 8MHz (checked by using this clock for timer) but MCLK
seems to
>>
>> run
>>
>>>at the DCO frequency because I don't see any improvement in
processing
>>>speed.
>>>
>>>-----Oorspronkelijk bericht-----
>>>Van: Richard F. Tennis [mailto:RTennis@RTen...]
>>>Verzonden: maandag 2 augustus 2004 16:36
>>>Aan: msp430@msp4...
>>>Onderwerp: Re: [msp430] MCLK sourced from XT2
>>>
>>>
>>>Adriano,
>>>
>>>Here is some C code that works for me:
>>>
>>> WDTCTL = WDTPW + WDTHOLD; // Stop WDT
>>>
>>> BCSCTL1 &= ~XT2OFF; // Turn on XT2
>>> do {
>>>// Wait for XT2 to stablize
>>> IFG1 &= ~OFIFG; // Clear OSCFault flag
>>> for (i = 0xFFF; i > 0; i--); // Time for flag to set
>>> } while ((IFG1 & OFIFG) == OFIFG); // OSCFault flag still
>>>set?
>>> BCSCTL2 |= SELM1+SELS; // Switch to XT2 for
MCLK and
>>
>> SMCLK
>>
>>>Richard.
>>>
>>>Adriano Pegoraro Caye wrote:
>>>
>>>
>>>
>>>>Looking at the piece of code provided, I've seen no delay
for clock
>>>>stabilization. Have you provided it? It's important to
generate such
>delay
>>>>before changing the clock source from DCO to XT2, at least it
says so
>>>>in the
>>>>MSP430x1xx User's Guide. Probably that 6-MHz frequency on
the MCLK comes
>>>
>>>>from the DCO, and not the XT2.
>>>
>>>>Adriano.
>>>>
>>>>----- Original Message -----
>>>>From: Sipke de Leeuw <s.de.leeuw@s.de...>
>>>>To: <msp430@msp4...>
>>>>Sent: Monday, August 02, 2004 5:46 AM
>>>>Subject: [msp430] MCLK sourced from XT2
>>>>
>>>>
>>>>
>>>>
>>>>>Hi,
>>>>>
>>>>>I have exactly the same problem here. My MSP430F449 MCLK
refuses to use
>>>>
>>>>the
>>>>
>>>>
>>>>>XT2 clock. Also the SMCLK does use the XT2 clock without
problems. I use
>>>>>this clock for UART and other timers.
>>>>>
>>>>>Sipke
>>>>>
>>>>>
>>>>>
>>>>>-----Oorspronkelijk bericht-----
>>>>>Van: mspgcc-users-admin@mspg...
>>>>>[mailto:mspgcc-users-admin@mspg...]Namens Sebastien Taylor
>>>>>Verzonden: donderdag 22 juli 2004 0:20
>>>>>Aan: mspgcc-users@mspg...
>>>>>Onderwerp: [Mspgcc-users] MCLK sourced from XT2
>>>>>
>>>>>
>>>>>Hello, I am having a strange problem getting the MCLK to
work with an
>>>>>external 8Mhz XT2. I've set it up along with SMCLK to
source from the
>>>>>XT2, and SMCLK works great at 8Mhz, but the MCLK will only
run at 6Mhz.
>>>>> Does anyone have any ideas?
>>>>>
>>>>>_BIS_SR(OSCOFF); /* Disable LFXT1CLK (32Khz) */
>>>>>SCFI0 = FN_8;
>>>>>FLL_CTL1 = SELM_XT2 | SELS;
>>>>>P1DIR = 0x12;
>>>>>P1SEL = 0x12;
>>>>>
>>>>>
>>>>>Thanks for any help.
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>
>>>>>.
>>>>>
>>>>>
>>>>>>.
>>>>
>>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>.
>>>
>>>
>>>Yahoo! Groups Links
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>
>>>.
>>>
>>>
>>>Yahoo! Groups Links
>>>
>>>
>>>
>>>
>>>
>>>
>>
>>
>>
>>
>>
>> .
>>
>>
>> Yahoo! Groups Links
>>
>>
>>
>>
>>
>>
>>
>>
>>
>>
>> .
>>
>>
>> Yahoo! Groups Links
>>
>>
>>
>>
>>
>>
>.
>Yahoo! Groups Links
>.
>
>Yahoo! Groups Links
>
