Mario Ivancic schreef op 24-Feb-14 8:35 PM:
>
> Hello,
>
> I have custom linker script and custom crt0.S. Everything from crt0.S
> goes before code read protection word.
> For cortex-m3 crt0.S I have:
> vector table (first part)
> vector table checksum
> vector table (second part)
> Reset Handler
> abort function
> do_nothing_and_return function
> Default_Exception_Handler
> Default_IRQ_Handler
> HardFault_Handler
> 32 bytes for serial number
> code_read_protection_word
>
> With this setup I have few unused bytes but I don't consider it a
issue.
>
I understand that by going to the trouble of project-specific tweaking
you can find a use for that fragment of FLASH. What I don't understand
is why they didn't select a word immediately after the (more or less
mandatory) vector table to save us from such trouble!
Wouter
Unable to compile the freeRTOS demo downloaded from this group
Started by ●February 22, 2014
Reply by ●February 24, 20142014-02-24
Reply by ●February 24, 20142014-02-24
Wouter,
the location you suggest is occupied by an existing peripheral interrupt
vector. They could have used an undefined exception (specific to the core,
before the interrupt vectors), with the risk that another core would use it
(risk is extremely low and it would be another chip alltogether... but
still).
But the question is valid.
Cheers
Olivier Gautherot
o...@gautherot.net
Cel:+56 98 730 9361
www.gautherot.net
http://www.linkedin.com/in/ogautherot
On Mon, Feb 24, 2014 at 5:59 PM, Wouter van Ooijen wrote:
> Mario Ivancic schreef op 24-Feb-14 8:35 PM:
>
> Hello,
>
> I have custom linker script and custom crt0.S. Everything from crt0.S goes
> before code read protection word.
> For cortex-m3 crt0.S I have:
> vector table (first part)
> vector table checksum
> vector table (second part)
> Reset Handler
> abort function
> do_nothing_and_return function
> Default_Exception_Handler
> Default_IRQ_Handler
> HardFault_Handler
> 32 bytes for serial number
> code_read_protection_word
>
> With this setup I have few unused bytes but I don't consider it a issue.
> I understand that by going to the trouble of project-specific tweaking
> you can find a use for that fragment of FLASH. What I don't understand is
> why they didn't select a word immediately after the (more or less
> mandatory) vector table to save us from such trouble!
>
> Wouter
>
>
>
the location you suggest is occupied by an existing peripheral interrupt
vector. They could have used an undefined exception (specific to the core,
before the interrupt vectors), with the risk that another core would use it
(risk is extremely low and it would be another chip alltogether... but
still).
But the question is valid.
Cheers
Olivier Gautherot
o...@gautherot.net
Cel:+56 98 730 9361
www.gautherot.net
http://www.linkedin.com/in/ogautherot
On Mon, Feb 24, 2014 at 5:59 PM, Wouter van Ooijen wrote:
> Mario Ivancic schreef op 24-Feb-14 8:35 PM:
>
> Hello,
>
> I have custom linker script and custom crt0.S. Everything from crt0.S goes
> before code read protection word.
> For cortex-m3 crt0.S I have:
> vector table (first part)
> vector table checksum
> vector table (second part)
> Reset Handler
> abort function
> do_nothing_and_return function
> Default_Exception_Handler
> Default_IRQ_Handler
> HardFault_Handler
> 32 bytes for serial number
> code_read_protection_word
>
> With this setup I have few unused bytes but I don't consider it a issue.
> I understand that by going to the trouble of project-specific tweaking
> you can find a use for that fragment of FLASH. What I don't understand is
> why they didn't select a word immediately after the (more or less
> mandatory) vector table to save us from such trouble!
>
> Wouter
>
>
>
Reply by ●February 24, 20142014-02-24
Olivier Gautherot schreef op 24-Feb-14 10:06 PM:
> Wouter,
>
> the location you suggest is occupied by an existing peripheral
> interrupt vector. They could have used an undefined exception
> (specific to the core, before the interrupt vectors), with the risk
> that another core would use it (risk is extremely low and it would be
> another chip alltogether... but still).
>
My idea would be to use the first location that is not claimed for any
special purpose.
...
No, don't tell me 0x02FC is the first such location?!?!
Wouter
> Wouter,
>
> the location you suggest is occupied by an existing peripheral
> interrupt vector. They could have used an undefined exception
> (specific to the core, before the interrupt vectors), with the risk
> that another core would use it (risk is extremely low and it would be
> another chip alltogether... but still).
>
My idea would be to use the first location that is not claimed for any
special purpose.
...
No, don't tell me 0x02FC is the first such location?!?!
Wouter
Reply by ●February 24, 20142014-02-24
It seems to me that there is a perfectly reasonable explanation.
A bunch of engineers were sitting around a bar table eating pizza and drinking beer when they came up with the idea that by placing the constant up away from the vectors, they could separate system designers into two classes: Those that could figure it out, would probably complain about it, but wouldn't completely mess up the chip. Or, those who couldn't figure it out and shouldn't be playing with CRP anyway because they'll brick the chip right out of the gate.
I never overlook the pizza and beer explanation for design issues!
Richard
A bunch of engineers were sitting around a bar table eating pizza and drinking beer when they came up with the idea that by placing the constant up away from the vectors, they could separate system designers into two classes: Those that could figure it out, would probably complain about it, but wouldn't completely mess up the chip. Or, those who couldn't figure it out and shouldn't be playing with CRP anyway because they'll brick the chip right out of the gate.
I never overlook the pizza and beer explanation for design issues!
Richard
Reply by ●February 24, 20142014-02-24
Richard, LOL!!!
@Wouter, seriously, the CRP scheme is not for a single chip so I guess they
tried to make it a generic solution. My guess is that it should support
different cores so it would not be advisable to reuse one of the exceptions
vectors - this leaves out vectors 0 to 15. In addition, the NVIC can
support up to 240 interrupts, what would give us a maximum table size of
256 (or address 0x400 for the CRP). By using 0x2FC as address for the CRP,
they are deliberately limiting the number of interrupts to 174, which
sounds reasonable for a general purpose chip (most chips should be in the
order of 30 to 50). I suppose Marketing decided that address 0x1FC would
leave 110 available interrupts and would be a bit tight on the edges.
I'm not sure I have any more intelligent answer to give you :-)
Cheers
Olivier Gautherot
o...@gautherot.net
Cel:+56 98 730 9361
www.gautherot.net
http://www.linkedin.com/in/ogautherot
On Mon, Feb 24, 2014 at 8:03 PM, wrote:
> It seems to me that there is a perfectly reasonable explanation.
> A bunch of engineers were sitting around a bar table eating pizza and
> drinking beer when they came up with the idea that by placing the constant
> up away from the vectors, they could separate system designers into two
> classes: Those that could figure it out, would probably complain about it,
> but wouldn't completely mess up the chip. Or, those who couldn't figure it
> out and shouldn't be playing with CRP anyway because they'll brick the chip
> right out of the gate.
> I never overlook the pizza and beer explanation for design issues!
> Richard
>
>
>
@Wouter, seriously, the CRP scheme is not for a single chip so I guess they
tried to make it a generic solution. My guess is that it should support
different cores so it would not be advisable to reuse one of the exceptions
vectors - this leaves out vectors 0 to 15. In addition, the NVIC can
support up to 240 interrupts, what would give us a maximum table size of
256 (or address 0x400 for the CRP). By using 0x2FC as address for the CRP,
they are deliberately limiting the number of interrupts to 174, which
sounds reasonable for a general purpose chip (most chips should be in the
order of 30 to 50). I suppose Marketing decided that address 0x1FC would
leave 110 available interrupts and would be a bit tight on the edges.
I'm not sure I have any more intelligent answer to give you :-)
Cheers
Olivier Gautherot
o...@gautherot.net
Cel:+56 98 730 9361
www.gautherot.net
http://www.linkedin.com/in/ogautherot
On Mon, Feb 24, 2014 at 8:03 PM, wrote:
> It seems to me that there is a perfectly reasonable explanation.
> A bunch of engineers were sitting around a bar table eating pizza and
> drinking beer when they came up with the idea that by placing the constant
> up away from the vectors, they could separate system designers into two
> classes: Those that could figure it out, would probably complain about it,
> but wouldn't completely mess up the chip. Or, those who couldn't figure it
> out and shouldn't be playing with CRP anyway because they'll brick the chip
> right out of the gate.
> I never overlook the pizza and beer explanation for design issues!
> Richard
>
>
>
