Designing Embedded Systems with FPGA-2
In last part, we created hardware design of basic system. The next step is to generate (compile) hardware design. Compiled hardware design is known as bit-stream andstored in *.bit file. To compile hardware, use hardware->generate hardware tab. The complete hardware design generation takes several seconds to several minutes depending on computer speed and design complexity. In back ground, the whole design process involves many different steps including synthesis, placement, routing and run time checking. If we use VHDL to write and generate hardware design, we must follow all these steps in sequence, but Xilinx EDK is making life easier for embedded system by executing all these steps in sequence in background.
Compilation generates design report and stored in system.map.mrp file and displayed in output part of console window that looks like,
analysis completed Tue Oct 30 20:18:40 2007
Generating Report ...
Number of warnings: 0
Number of info messages: 2
Total time: 5 secs
cd implementation; bitgen -w -f bitgen.ut system
Release 9.1.02i - Bitgen J.33
Copyright (c) 1995-2007 Xilinx, Inc.All rights reserved.
Loading device for application Rf_Device from file '3s500e.nph' in environment
"system" is an NCD, version 3.1, device xc3s500e, package fg320, speed -4
Opened constraints file system.pcf.
Tue Oct 30 20:18:43 2007
DRC detected 0 errors and 0 warnings.
Creating bit map...
Saving bit stream in "system.bit".
Bitstream generation is complete.
Once hardware design get finished, we need to generate software libraries and board support package using software->Generate Libraries and BSPs tab. (Use following screen for reference). If you look in your project folder *.mhs is hardware description file and *.mss is software description file used for generation.
and message in output window is,
Libraries generated in D:\FPGA\BookSample1\microblaze_0\lib\ directory
Running execs_generate for OS'es, Drivers and Libraries ...
The final step is to compile software for applications for testing memory and peripheral created by base system builder wizard. Use software->Build All User Applications tab to compile software applications. EDK uses GCC to compile software applications written for Microblaze.
If you look at Application tab in project information area (or project explorer), you will see two defaults and two projects. We will not discuss about defaults. Out of two projects, TestApp_Memory is marked green and TestApp_Peripheral is marked with cross (see following pic.)
So out of two projects TestApp_Memory is marked to go in default memory which starts from 0x0 location and will run immediately after reset of processor. Other projects share memory but not placed from 0x0. To execute such projects, software controlled execution point transfer is required. We will learn more about that later on. So be ready to get result from first basic design next time.
Previous post by Pragnesh Patel:
Designing Embedded System with FPGA - 1
We Gill Instruments Pvt. Ltd. have a requirement for an engineer with a strong expertise and hands on experience in the field of MSP430. Candidates who are willing to relocate in Bangalore can send us their CV on - firstname.lastname@example.org.
To post reply to a comment, click on the 'reply' button attached to each comment. To post a new comment (not a reply to a comment) check out the 'Write a Comment' tab at the top of the comments.
Registering will allow you to participate to the forums on ALL the related sites and give you access to all pdf downloads.