Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
Introduction
This article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product. The Multi-Channel Asynchronous Receiver (MCAR) FPGA core developed for that product will be used to illustrate the technique(s) needed to fit a 16 channel MCAR into a single Spartan II XC2S30-5VQ100 FPGA.
To stay true to the original design, I...
Use Microprogramming to Save Resources and Increase Functionality
IntroductionMicroprogramming is a design approach that every FPGA designer should have in their bag of tricks. I subscribe to the concept that microprogramming is a structured approach to the design of state machines. This is essentially the view of Maurice Wilkes when he first proposed microprogramming in 1951 as an alternative method for the implementation of the control section of a computer. Wilkes was interested in improving the reliability and reducing time needed to implement...
How FPGAs work, and why you'll buy one
Today, pretty much everyone has a CPU, a DSP and a GPU, buried somewhere in their PC, phone, car, etc. Most don't know or care that they bought any of these, but they did.
Will everyone, at some future point, also buy an FPGA? The market size of FPGAs today is about 1% of the annual global semiconductor sales (~$3B vs ~$300B). Will FPGA eventually...
ANSI-C to VHDL compiler
Ylichron has announced the availability of "ANSI-C to VHDL" compiler. This is claimed to be first such compiler.
Designing Embedded Systems with FPGA-2
In last part, we created hardware design of basic system. The next step is to generate (compile) hardware design. Compiled hardware design is known as bit-stream andstored in *.bit file. To compile hardware, use hardware->generate hardware tab. The complete hardware design generation takes several seconds to several minutes depending on computer speed and design complexity. In back ground, the whole design process involves many different steps including synthesis, placement, routing and...
Designing Embedded System with FPGA - 1
With the introduction of soft processors and related tools (like EDK from Xilinx), implementation of basic embedded system in FPGA is made easy. This requires very little or almost no knowledge of VHDL programming. Actually that’s how I started. If user is interested in taking full advantage of FPGA and its parallel processing power, then yes, detail understanding of soft processor, its peripheral bus and VHDL programming is required.
I will start with...
My first entry to embeddedrelated.com
Hello everybody, it’s nice to have an opportunity to write on embedded system and share experiments with readers.
I recently started embedded systems in FPGA having luxury of reconfigurable logics and will like to share some of my thoughts in first post.
I worked with Xilinx SPARTAN 3E and with their embedded system tools known as EDK 9.1 (Embedded Development Kit) software tool, its fun to play with FPGA with no knowledge of VHDL programming. In order to create hardware logic block...
How FPGAs work, and why you'll buy one
Today, pretty much everyone has a CPU, a DSP and a GPU, buried somewhere in their PC, phone, car, etc. Most don't know or care that they bought any of these, but they did.
Will everyone, at some future point, also buy an FPGA? The market size of FPGAs today is about 1% of the annual global semiconductor sales (~$3B vs ~$300B). Will FPGA eventually...
Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
IntroductionThis article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product. The Multi-Channel Asynchronous Receiver (MCAR) FPGA core developed for that product will be used to illustrate the technique(s) needed to fit a 16 channel MCAR into a single Spartan II XC2S30-5VQ100 FPGA.
To stay true to the original design, I...
Use Microprogramming to Save Resources and Increase Functionality
IntroductionMicroprogramming is a design approach that every FPGA designer should have in their bag of tricks. I subscribe to the concept that microprogramming is a structured approach to the design of state machines. This is essentially the view of Maurice Wilkes when he first proposed microprogramming in 1951 as an alternative method for the implementation of the control section of a computer. Wilkes was interested in improving the reliability and reducing time needed to implement...
Designing Embedded System with FPGA - 1
With the introduction of soft processors and related tools (like EDK from Xilinx), implementation of basic embedded system in FPGA is made easy. This requires very little or almost no knowledge of VHDL programming. Actually that’s how I started. If user is interested in taking full advantage of FPGA and its parallel processing power, then yes, detail understanding of soft processor, its peripheral bus and VHDL programming is required.
I will start with...
ANSI-C to VHDL compiler
Ylichron has announced the availability of "ANSI-C to VHDL" compiler. This is claimed to be first such compiler.My first entry to embeddedrelated.com
Hello everybody, it’s nice to have an opportunity to write on embedded system and share experiments with readers.
I recently started embedded systems in FPGA having luxury of reconfigurable logics and will like to share some of my thoughts in first post.
I worked with Xilinx SPARTAN 3E and with their embedded system tools known as EDK 9.1 (Embedded Development Kit) software tool, its fun to play with FPGA with no knowledge of VHDL programming. In order to create hardware logic block...
Designing Embedded Systems with FPGA-2
In last part, we created hardware design of basic system. The next step is to generate (compile) hardware design. Compiled hardware design is known as bit-stream andstored in *.bit file. To compile hardware, use hardware->generate hardware tab. The complete hardware design generation takes several seconds to several minutes depending on computer speed and design complexity. In back ground, the whole design process involves many different steps including synthesis, placement, routing and...
How FPGAs work, and why you'll buy one
Today, pretty much everyone has a CPU, a DSP and a GPU, buried somewhere in their PC, phone, car, etc. Most don't know or care that they bought any of these, but they did.
Will everyone, at some future point, also buy an FPGA? The market size of FPGAs today is about 1% of the annual global semiconductor sales (~$3B vs ~$300B). Will FPGA eventually...
Use Microprogramming to Save Resources and Increase Functionality
IntroductionMicroprogramming is a design approach that every FPGA designer should have in their bag of tricks. I subscribe to the concept that microprogramming is a structured approach to the design of state machines. This is essentially the view of Maurice Wilkes when he first proposed microprogramming in 1951 as an alternative method for the implementation of the control section of a computer. Wilkes was interested in improving the reliability and reducing time needed to implement...
Designing Embedded System with FPGA - 1
With the introduction of soft processors and related tools (like EDK from Xilinx), implementation of basic embedded system in FPGA is made easy. This requires very little or almost no knowledge of VHDL programming. Actually that’s how I started. If user is interested in taking full advantage of FPGA and its parallel processing power, then yes, detail understanding of soft processor, its peripheral bus and VHDL programming is required.
I will start with...
Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver
IntroductionThis article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product. The Multi-Channel Asynchronous Receiver (MCAR) FPGA core developed for that product will be used to illustrate the technique(s) needed to fit a 16 channel MCAR into a single Spartan II XC2S30-5VQ100 FPGA.
To stay true to the original design, I...
Designing Embedded Systems with FPGA-2
In last part, we created hardware design of basic system. The next step is to generate (compile) hardware design. Compiled hardware design is known as bit-stream andstored in *.bit file. To compile hardware, use hardware->generate hardware tab. The complete hardware design generation takes several seconds to several minutes depending on computer speed and design complexity. In back ground, the whole design process involves many different steps including synthesis, placement, routing and...
ANSI-C to VHDL compiler
Ylichron has announced the availability of "ANSI-C to VHDL" compiler. This is claimed to be first such compiler.My first entry to embeddedrelated.com
Hello everybody, it’s nice to have an opportunity to write on embedded system and share experiments with readers.
I recently started embedded systems in FPGA having luxury of reconfigurable logics and will like to share some of my thoughts in first post.
I worked with Xilinx SPARTAN 3E and with their embedded system tools known as EDK 9.1 (Embedded Development Kit) software tool, its fun to play with FPGA with no knowledge of VHDL programming. In order to create hardware logic block...
