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Hi list, Does anyone out there know if there are any issues with a slow rise time on VDD for the HCS12 processor family (D64 processor in particular)? I haven't found anything about it in the datasheet. Due to the large amount of capacitance on the power bus in one of our systems, the 12V supply rises slowly, hence the output of the 5V regulator also rises slowly. It takes about 15 ms to get from 0 to 4.75 volts. Is there any reason that this should upset the processor? We're having trouble getting it to acknowledge BDM communication at power up, though it always seems to execute code correctly once we finally get it loaded. The clock looks to be running fine. Oh yeah, the reset line is held firmly low until VDD has been at 5 volts (+/- 100 mv, maybe) for 800 us or so. Thoughts appreciated, Pat |
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Power supply rise time
Started by ●April 11, 2003
Reply by ●April 13, 20032003-04-13
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Pat, Here are a few possible causes for your BDM startup problems: 1) Make sure nothing interferes with the Reset coming from the BDM connector. It should be connected directly to your HCS12 CPU in order to Reset, and un-Reset it when it needs to. 2) A BDM must bring up the HCS12 CPU in Special Single Chip mode first, and can then switch to any desired operating mode by writing to some internal registers. In order for this to happen, it is required that MODA and MODB will be held low during Reset. If you have something to drive one of these signals high during Reset, you will have problems. If you have nothing connected to MODA and MODB, they will be held low during Reset by internal HCS12 pull-down resistors that are enabled during Reset. 3) The BKGD pin should be connected directly from the BDM connector to the CPU. Hope this helps, Doron Nohau Corporation HC12 In-Circuit Emulators www.nohau.com/emul12pc.html At 01:36 PM 4/11/2003 -0600, you wrote: >Hi list, > >Does anyone out there know if there are any issues with a slow rise time >on VDD for >the HCS12 processor family (D64 processor in particular)? I haven't found >anything >about it in the datasheet. > >Due to the large amount of capacitance on the power bus in one of our >systems, the >12V supply rises slowly, hence the output of the 5V regulator also rises >slowly. It >takes about 15 ms to get from 0 to 4.75 volts. Is there any reason that >this should >upset the processor? We're having trouble getting it to acknowledge BDM >communication at power up, though it always seems to execute code >correctly once we >finally get it loaded. The clock looks to be running fine. Oh yeah, the >reset line >is held firmly low until VDD has been at 5 volts (+/- 100 mv, maybe) for >800 us or >so. > >Thoughts appreciated, > >Pat |
Reply by ●April 14, 20032003-04-14
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Thanks for the ideas, however I don't think any of them are the current
problem. The Reset line goes from the BDM connector to the processor and to a resistor to a Motorola MC33989 System Basis Chip to control the reset. I removed the resistor to the SBC to no avail. Except that the board wouldn't run properly WITHOUT the debugger connected anymore -- as you might expect with a slow VDD rise, the reset line goes high before VDD is up so maybe we don't get a clean reset. Not a problem with the SBC reconnected. By the way, the identical circuitry works fine on two other boards that don't have the slow VDD rise (and they use H256 or DP256 processors instead of D64). MODA and MODB are tied to ground and not used for any other purpose. There is a 10K pullup resistor on the BDM line. I tried it with and without the resistor and there's no difference. One more thing: Once we finally do get code loaded into the processor, if not only runs fine, but seems to be easier to reprogram. It can take 10 tries and a bunch of manual resets to get the debugger running the first time, but rarely more than three tries to load revised code into the processor. This behavior has been consistent through eight boards now!! I'm baffled. On the bright side, it doesn't really seem to have anything to do with a slow VDD rise time. That's good, 'cause I had NO idea how to fix that! thanks, Pat Doron Fael wrote: > Pat, > > Here are a few possible causes for your BDM startup problems: > > 1) > Make sure nothing interferes with the Reset coming from the BDM connector. > It should be connected directly to your HCS12 CPU in order to Reset, and > un-Reset it when it needs to. > > 2) > A BDM must bring up the HCS12 CPU in Special Single Chip mode first, and > can then switch to any desired operating mode by writing to some internal > registers. In order for this to happen, it is required that MODA and MODB > will be held low during Reset. If you have something to drive one of these > signals high during Reset, you will have problems. If you have nothing > connected to MODA and MODB, they will be held low during Reset by internal > HCS12 pull-down resistors that are enabled during Reset. > > 3) > The BKGD pin should be connected directly from the BDM connector to the CPU. > > Hope this helps, > Doron > Nohau Corporation > HC12 In-Circuit Emulators > www.nohau.com/emul12pc.html > > At 01:36 PM 4/11/2003 -0600, you wrote: > > >Hi list, > > > >Does anyone out there know if there are any issues with a slow rise time > >on VDD for > >the HCS12 processor family (D64 processor in particular)? I haven't found > >anything > >about it in the datasheet. > > > >Due to the large amount of capacitance on the power bus in one of our > >systems, the > >12V supply rises slowly, hence the output of the 5V regulator also rises > >slowly. It > >takes about 15 ms to get from 0 to 4.75 volts. Is there any reason that > >this should > >upset the processor? We're having trouble getting it to acknowledge BDM > >communication at power up, though it always seems to execute code > >correctly once we > >finally get it loaded. The clock looks to be running fine. Oh yeah, the > >reset line > >is held firmly low until VDD has been at 5 volts (+/- 100 mv, maybe) for > >800 us or > >so. > > > >Thoughts appreciated, > > > >Pat > > > -------------------- > > ">http://docs.yahoo.com/info/terms/ |
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Reply by ●April 14, 20032003-04-14
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At 08:58 AM 4/14/2003 -0600, you wrote: >The Reset line goes from the BDM connector to the processor and to a >resistor to a Motorola MC33989 System Basis Chip to control the reset. I >removed the >resistor to the SBC to no avail. Except that the board wouldn't run properly >WITHOUT the debugger connected anymore -- as you might expect with a slow VDD >rise, the reset line goes high before VDD is up so maybe we don't get a clean >reset. I don't know if this will be ANY help at all, but... Your problem sounds vaguely familiar. Many years ago we had a problem with HC11's in a banking terminal design. Essentially a printer would jam and drag down the power. The monitor chip would force a reset and *usually* everything would be fine. But sometimes the power would come up slowly, especially just before it got to the point where RESET was released by the monitor chip. [A "brown out" could produce similar results.] Unfortunately, I don't recall all the details, but basically it was a design oversight in the reset circuitry in the chip. The HC11 would not go to the correct interrupt vector (i.e. the RESET FFFE vector) and the chip would not start cleanly. Holding the reset line low longer, even after Vdd was a nice stable 5 volts, would NOT help. Essentially, the RESET line needed to hold more circuitry in the HC11 than it did. After lengthy discussions and verification with Motorola engineers (and to their credit, they were willing to spend effort to reproduce our results), it was decided that the solution would involve a significant design change to the HC11 and would not be fixed. We basically had to put circuitry on our board to keep Vdd from betting to the HC11 until it was up and stable. [High side FET] Sounds remarkably similar to what you are seeing. Wonder if the same folks designed the RESET and startup logic in the HC11 and HC12? <G> jmk ----------- James M. Knox TriSoft ph 512-385-0316 1109-A Shady Lane fax 512-366-4331 Austin, Tx 78721 ----------- |
Reply by ●April 23, 20032003-04-23
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On some designs that I have done, I have encountered, microprocessor start problems from slow rise times of the power supply even when using a reset controller. When analysed they have had three basic causes: 1) The most common one is that a component, sometimes the micro, sometimes some other VLSI component, still has problems at the trip voltage of the reset controller. I have fixed this by changing the voltage threshold of the reset circuit by using a resistive divider cct, or by increasing the reset time. 2) Occasionally I have chosen the wrong reset chip, ie one with too short a reset pulse width or the wrong voltage threshold. 3) I have used a crystal oscillator cct that needs a minimum rise time of its Vcc line to start oscillating. The net result is that the micro doesn't get any clock, or the clock doesnt start enough time before the reset line rises. I have fixed this by changing the oscillator module, or by modifying the oscillator cct to start more quickly. I once saw a design that held the oscillator off until Vcc got to a few volts (by just using a zener in the bias path of the active element of the oscillator). David le Comte RF Technology Pty Ltd |
