USB 3.0 implementation on FPGA

On Mar 26, 8:32=A0pm, wojtek <wojtekpowiertow...@gmail.com> wrote:
> On Mar 26, 1:58=A0pm, Antti <antti.luk...@googlemail.com> wrote:
>
> > well, USB 3.0 is the first one that needs NO PHY
>
> > as the MGT's in some newer FPGA's are USB 3.0 capable directly
> > just wire MGT to usb 3.0 superspeed pins, and that about it
>
> > Antti
>
> That is the first time i hear abou MGT being compatible with USB 3.0
> PHY, but I haven't doing anything in USB 3.0 topic for almost a year.
> I must say I find it hard to believe thought, because USB 3.0 besides
> translating digital signal to differential analog signal also
> transmits USB 3.0 specific LFPS (low frequency pulse signaling) and
> from what I learned the USB 3.0 PHY was supposed to take care of that
> (just like latest PCI express PHY, which has similar LFPS technology).
> I believe the MGT doesn't support that. But as I've said I hadn't even
> researched it for some time, so I might be wrong.


USB 3.0 calls the "LFPS" now "OOB". Xilinx GTX transceivers have no
problem supporting that. Matter of fact we have a fully working USB
3.0
device IP Core running on Xilinx FPGAs.

One more note to the OP: In order to properly implement USB 3.0, you
would most likely need a protocol analyser, roughly a $50K
investment ...

Cheers,
rudi

On Mar 26, 7:58=A0am, Antti <antti.luk...@googlemail.com> wrote:
> well, USB 3.0 is the first one that needs NO PHY
>
> as the MGT's in some newer FPGA's are USB 3.0 capable directly
> just wire MGT to usb 3.0 superspeed pins, and that about it

I'm slightly confused by this statement.  If 3.0 requires fallback
capability, how could FPGA hardware be compatible with 3.0 without
being compatible with an earlier version, and if FPGA hardware IS
compatible with an earlier version, how can you call 3.0 the first?

On 29/03/2010 06:00, Patrick Maupin wrote:
> On Mar 26, 7:58 am, Antti<antti.luk...@googlemail.com>  wrote:
>> well, USB 3.0 is the first one that needs NO PHY
>>
>> as the MGT's in some newer FPGA's are USB 3.0 capable directly
>> just wire MGT to usb 3.0 superspeed pins, and that about it
>
> I'm slightly confused by this statement.  If 3.0 requires fallback
> capability, how could FPGA hardware be compatible with 3.0 without
> being compatible with an earlier version, and if FPGA hardware IS
> compatible with an earlier version, how can you call 3.0 the first?

The compatibility arises because USB 3.0 uses a new connector that has 
both USB 2.0 connections and the new (SuperSpeed) connections.

	Andrew