On Jan 4, 5:19=A0pm, rickman <gnu...@gmail.com> wrote:> > I'm not sure what your 1 uA figure refers to. =A0The document you linked to, uses 32.768Khz, so that was the data point I took the thread to apply to : 32.768KHz Crystals viz: 1-5uA is the ballpark for operational 32,768KHz oscillators.> MY need is for an > oscillator in the range of 300 kHz to 1 MHz. =A0If you buy a canned > oscillator they aren't drawing 1 uA. =A0The lowest I can find is 3 mA > and that is an all silicon unit.err, but 300KHz -1MHz is rather no-mans-land in Crystal terms ? Digikey lists 1MHz xtals at $17, and jumps to 307KHz ones at $5.00 ? Or, did you mean a Digital Ceramic Resonator Oscillator ? For ~455KHz Murata resonator, and 2V swing, a power budget of 10-20uA is reasonable. (and 0.3%-0.5% tolerance) -jg
Digital Crystal Oscillator
Started by ●December 27, 2010
Reply by ●January 4, 20112011-01-04
Reply by ●January 4, 20112011-01-04
In article <8oeprtF8sgU1@mid.individual.net>, Joerg <news@analogconsultants.com> wrote:> >But isn't it that they shun resistors? Then all they'd have is a dither >of the "gooser signal" and if that's quantized to 2.5nsec time slivers >they'll run up to a hard limit. IIUC the purpose is to coax the external >crystal into resonating for as long a time possible. Almost like trying >to make the champagne glasses on the shelf "sing" with just the right >blast from a trumpet :-)This is an asynchronous processor. 2.5 nsec is approximate granularity time for a software delay loop but that is only used for exciting the crystal. If the processor reacts to a level generated by a crystal, jitter is claimed to be in the picoseconds or less.> >-- >Regards, Joerg > >http://www.analogconsultants.com/ > >"gmail" domain blocked because of excessive spam. >Use another domain or send PM.-- -- Albert van der Horst, UTRECHT,THE NETHERLANDS Economic growth -- being exponential -- ultimately falters. albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst
Reply by ●January 4, 20112011-01-04
Albert van der Horst wrote:> In article <8oeprtF8sgU1@mid.individual.net>, > Joerg <news@analogconsultants.com> wrote: >> But isn't it that they shun resistors? Then all they'd have is a dither >> of the "gooser signal" and if that's quantized to 2.5nsec time slivers >> they'll run up to a hard limit. IIUC the purpose is to coax the external >> crystal into resonating for as long a time possible. Almost like trying >> to make the champagne glasses on the shelf "sing" with just the right >> blast from a trumpet :-) > > This is an asynchronous processor. 2.5 nsec is approximate granularity > time for a software delay loop but that is only used for exciting > the crystal. > If the processor reacts to a level generated by a crystal, jitter is > claimed to be in the picoseconds or less. >That I'd want to see :-) As the ancient forefathers said, hic Rhodos, hic salta. They should put some spectrum analyzer plots on the table. Claims alone ain't cutting it. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.
Reply by ●January 4, 20112011-01-04
In article <8oh2v0Fh18U2@mid.individual.net>, Joerg <news@analogconsultants.com> wrote:>Albert van der Horst wrote: >> In article <8oeprtF8sgU1@mid.individual.net>, >> Joerg <news@analogconsultants.com> wrote: >>> But isn't it that they shun resistors? Then all they'd have is a dither >>> of the "gooser signal" and if that's quantized to 2.5nsec time slivers >>> they'll run up to a hard limit. IIUC the purpose is to coax the external >>> crystal into resonating for as long a time possible. Almost like trying >>> to make the champagne glasses on the shelf "sing" with just the right >>> blast from a trumpet :-) >> >> This is an asynchronous processor. 2.5 nsec is approximate granularity >> time for a software delay loop but that is only used for exciting >> the crystal. >> If the processor reacts to a level generated by a crystal, jitter is >> claimed to be in the picoseconds or less. >> > >That I'd want to see :-) > >As the ancient forefathers said, hic Rhodos, hic salta. They should put >some spectrum analyzer plots on the table. Claims alone ain't cutting it.It doesn't work yet, so it is not a claim, it is what I expected. Probably too optimistic, indeed. Let's say 300 pS jitter, i.e. a third of the fastest instruction.>-- >Regards, JoergGroetjes Albert -- -- Albert van der Horst, UTRECHT,THE NETHERLANDS Economic growth -- being exponential -- ultimately falters. albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst
Reply by ●January 4, 20112011-01-04
On Jan 4, 2:11=A0pm, Albert van der Horst <alb...@spenarnc.xs4all.nl> wrote:> It doesn't work yet, so it is not a claim, it is what I expected. > Probably too optimistic, indeed. Let's say 300 pS jitter, i.e. > a third of the fastest instruction.Working chips in versions with 24, and 40 core were working as long as five years ago. The 24 code models that were put in USB sticks and given away for a couple of years didn't have access to I/O pins, but chips have also been on development boards for about five years. The 144 core chips in fab today do have changes from previous designs and have not returned from fab to be tested and characterized so specific performance details for those chips are not yet available. All that exists for those chips so far are cad simulations, but those simulations have proved quite accurate over the years. 300ps is a reasonable estimate of the latency of pin wake circuit. The processor goes from full sleep to full speed within 300ps of an external event on the pin. This might vary by as much as percent, and introduce about 3ps if jitter to the system. 300ps is reasonable estimate for latency but as an estimate for pin wake jitter it is off by a factor of about 100. It switches in about 300ps, speed tends to vary by about 1% not 100%. Best Wishes
Reply by ●January 4, 20112011-01-04
On Jan 4, 3:00=A0am, malcolm <malcolm...@gmail.com> wrote:> On Jan 4, 5:19=A0pm, rickman <gnu...@gmail.com> wrote: > > > > > I'm not sure what your 1 uA figure refers to. =A0 > > The document you linked to, uses 32.768Khz, so that was > the data point I took the thread to apply to : 32.768KHz Crystals > > viz: 1-5uA is the ballpark for operational 32,768KHz oscillators. > > > MY need is for an > > oscillator in the range of 300 kHz to 1 MHz. =A0If you buy a canned > > oscillator they aren't drawing 1 uA. =A0The lowest I can find is 3 mA > > and that is an all silicon unit. > > err, but 300KHz -1MHz is rather no-mans-land in Crystal terms ? > > Digikey lists 1MHz xtals at $17, and jumps to 307KHz ones at $5.00 ? > > Or, did you mean a Digital Ceramic Resonator Oscillator ? > > For ~455KHz Murata resonator, and 2V swing, a power budget of 10-20uA > is reasonable. =A0(and 0.3%-0.5% tolerance)Yeah, that's what I found about crystal freqs. You can buy them at 100's of kHz, but not from stock. I have no idea what power level is reasonable. Where did you get the number you came up with? 1 MHz is not too far from what I would like and is available as a crystal easily, 1.8432 MHz is another that is very common and very cheap, but every time you double the frequency, the power would double I expect. It certainly does in the processor. Rick
Reply by ●January 4, 20112011-01-04
On Jan 4, 4:44=A0pm, Jeff Fox <f...@ultratechnology.com> wrote:> On Jan 4, 2:11=A0pm, Albert van der Horst <alb...@spenarnc.xs4all.nl> > wrote: > > > It doesn't work yet, so it is not a claim, it is what I expected. > > Probably too optimistic, indeed. Let's say 300 pS jitter, i.e. > > a third of the fastest instruction. > > Working chips in versions with 24, and 40 core were working > as long as five years ago. =A0 =A0The 24 code models that were put > in USB sticks and given away for a couple of years didn't have > access to I/O pins, but chips have also been on development > boards for about five years. =A0 The 144 core chips in fab today > do have changes from previous designs =A0and have not > returned from fab to be tested and characterized so specific > performance details for those chips are not yet available. > All that exists for those chips so far are cad simulations, > but those simulations have proved quite accurate over > the years. > > 300ps is a reasonable estimate of the latency of pin wake > circuit. =A0The processor goes from full sleep to full speed > within 300ps of an external event on the pin. =A0This might > vary by as much as percent, and introduce about 3ps > if jitter to the system. > > 300ps is reasonable estimate for latency but as an estimate > for pin wake jitter it is off by a factor of about 100. =A0It switches > in about 300ps, speed tends to vary by about 1% not 100%. > > Best WishesHi Jeff, I think I have posted this here, but I'm not sure. I've been running simulations in Spice to see how a crystal will behave when operated in a manner similar to this. One thing I found is that when stimulus and monitoring is done with one pin, the actual threshold of the input is important. Typically this threshold is not well controlled. CMOS data sheets typically allow input threshold range to be 25% to 75% of Vdd or even 20% to 80% of Vdd. I don't know how much of this range is actually found in real devices. Do you have any idea what to expect for the range of input threshold? Rick
Reply by ●January 5, 20112011-01-05
In article <b193a963-a25f-45c8-8a1a-5de0bc5f24fd@k14g2000pre.googlegroups.com>, malcolm <malcolm132@gmail.com> wrote:>On Jan 4, 5:19=A0pm, rickman <gnu...@gmail.com> wrote: >> >> I'm not sure what your 1 uA figure refers to. =A0 > >The document you linked to, uses 32.768Khz, so that was >the data point I took the thread to apply to : 32.768KHz Crystals > >viz: 1-5uA is the ballpark for operational 32,768KHz oscillators. > >> MY need is for an >> oscillator in the range of 300 kHz to 1 MHz. =A0If you buy a canned >> oscillator they aren't drawing 1 uA. =A0The lowest I can find is 3 mA >> and that is an all silicon unit. > >err, but 300KHz -1MHz is rather no-mans-land in Crystal terms ? > >Digikey lists 1MHz xtals at $17, and jumps to 307KHz ones at $5.00 ? > >Or, did you mean a Digital Ceramic Resonator Oscillator ? > >For ~455KHz Murata resonator, and 2V swing, a power budget of 10-20uA >is reasonable. (and 0.3%-0.5% tolerance)The people at green arrays calculate differently. They sum the energy needed for a computation, i.e. useful work. They use pJ which amounts to 1V 1 uA during 1 uS. So in the case of the 32 khz crystal: wake up itself : X pJ instruction one : Y pJ ..... instruction five: Y pJ instruction wait-for-pin : Z pJ total say : XXX pJ This is the cost of one cycle to be expended 32,000 time each second. Then the processor goes to sleep which takes 7.5 nA which drains the battery at the rate of 1.8 * 7.5 nAV = 13500 pJ/second Here you have to add the energy budget for driving the crystal which is quite possibly the largest of all. So you can see the motivation to keep the extra circuitry down. P.S. The Ah li-ion accu of my Nokia cell phone contains 11,764,000,000,000,000 pJ> >-jg > >-- -- Albert van der Horst, UTRECHT,THE NETHERLANDS Economic growth -- being exponential -- ultimately falters. albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst
Reply by ●January 5, 20112011-01-05
In article <3ec31eb2-736f-46c1-8495-38706827668b@d8g2000yqf.googlegroups.com>, rickman <gnuarm@gmail.com> wrote:>On Dec 27, 2:55 am, Tim Wescott <t...@seemywebsite.com> wrote: >> On Sun, 26 Dec 2010 20:46:26 -0800, rickman wrote: >> > I've read the Green Arrays web page app note on using a pin to turn a >> > crystal into an oscillator at >> >> >http://www.greenarrays.com/home/documents/pub/AP002-OSC.html >> >> > Although the work they did seems to work well enough, they stopped >> > working on the project a long way short of having an actual oscillator. >> > I've been trying to run a spice simulation to explore this concept and >> > finding that an oscillator is not so easy to design... as I already >> > knew. >> >> > Has anyone designed what I would call a digital crystal oscillator >> > before? Using Google I didn't find anything that actually uses digital >> > logic, or in this case software to act as the amplifier of a crystal >> > oscillator. Many designs use an inverter as an amplifier, either from a >> > digital logic chip or contained within a digital chip like a MCU. But I >> > can't seem to find any mention of an oscillator that uses a "kick" from >> > a truly digital controller. >> >> > From the simulations I have done, I am finding it hard to create just >> > the right conditions to make this idea work. Anyone know anything about >> > how to make a crystal oscillate using a digital drive controller? >> >> Either they never got it working, or they suddenly realized in all their >> babbling about "making extra components do their work" that they were >> replacing --> one stinking transistor <-- with a bazzilion of them. >> >> From the general tone of the article, either they don't know what the >> heck they're doing, or they're _really_ talking down to the audience. >> Their surprise at needing to give a crystal -- famous for being a Really >> High Q Device -- lots of cycles of excitation before they see an output >> tends to indicate happy ignorance rather than arrogant competence. >> >> If they were driving the pin directly into the crystal at its series >> resonant frequency they were probably way over-exciting it. >> >> Making a single-pin crystal oscillator is probably doable. Particularly >> if you're willing to go for the crystal's parallel resonance mode, you >> should be able to set up a pure negative resistance at a pin, turn it on, >> and stand back. Figuring out the complications is, of course, left as an >> exercise to the reader. >> >> --http://www.wescottdesign.com > >I've spent some more time with the simulation looking at alternative >ways to make it work and I'm pretty sure a single pin for stimulation >and observation is not practical. The problem is that the input >threashold is not set exactly in the center of the power-ground >range. Any displacement causes the two pushes (positive or negative) >to unbalance and move the bias point in the opposite direction of the >threashold. With even a modest offset in the threshold the >oscillations end up not crossing the threashold and operation stops.I don't argue with the need to keep things symmetric. I had a private exchange with GreenArrays and Greg Baily literally says: "At any rate the working oscillator once started is trivial" This has drawn my attention to a point you seem to have missed. Look at the document F18 I/O where it says pin wakeup. You can wait for either polarity change! So you can wait for it to be up and yank the output one way, and then you can wait for it to be down and yank it the other way. This should take care of your unbalance problem. As others have pointed out the real problem is to get things started with a higher frequency crystal like 1 Mhz. The Q is too high so that it is very difficult to hit the exact right frequency.> >I'm going to explore a two pin approach.I hope you give the one pin another shot.> >RickGroetjes Albert -- -- Albert van der Horst, UTRECHT,THE NETHERLANDS Economic growth -- being exponential -- ultimately falters. albert@spe&ar&c.xs4all.nl &=n http://home.hccnet.nl/a.w.m.van.der.horst
Reply by ●January 5, 20112011-01-05
Jeff Fox wrote:> On Jan 4, 2:11 pm, Albert van der Horst <alb...@spenarnc.xs4all.nl> > wrote: >> It doesn't work yet, so it is not a claim, it is what I expected. >> Probably too optimistic, indeed. Let's say 300 pS jitter, i.e. >> a third of the fastest instruction. > > Working chips in versions with 24, and 40 core were working > as long as five years ago. The 24 code models that were put > in USB sticks and given away for a couple of years didn't have > access to I/O pins, but chips have also been on development > boards for about five years. The 144 core chips in fab today > do have changes from previous designs and have not > returned from fab to be tested and characterized so specific > performance details for those chips are not yet available. > All that exists for those chips so far are cad simulations, > but those simulations have proved quite accurate over > the years. > > 300ps is a reasonable estimate of the latency of pin wake > circuit. The processor goes from full sleep to full speed > within 300ps of an external event on the pin. This might > vary by as much as percent, and introduce about 3ps > if jitter to the system. > > 300ps is reasonable estimate for latency but as an estimate > for pin wake jitter it is off by a factor of about 100. It switches > in about 300ps, speed tends to vary by about 1% not 100%. >Ok, that would be for the first cycle, the wake-up. However, how much stuff is going to happen in terms of processing until the chip performs the next crystal goosing if it deems it to be necessary, from first wake-up to applying current to this pin? In an asynchronous processor (sans clock) the latencies and thus phase noise effects can add up quickly. This can be simulated until the cows come home but the only way to really find out is to hang a good spectrum analyzer to this pin. Use at least a 10dB step attenuator in order not to fry in, and a FET probe of course. -- Regards, Joerg http://www.analogconsultants.com/ "gmail" domain blocked because of excessive spam. Use another domain or send PM.
