Hi all, Supposing AVR is a configured as a Master SPI device. Is it possible to discard AVR master SCK output signal and make SCK as an input in order to apply external bitstream clock. My app is connecting a Quad voice A/MU law Codec (MSM7705) to an AVR SPI bus. Many thanks
ATmega SPI question
Started by ●March 14, 2005
Reply by ●March 14, 20052005-03-14
habib bouaziz-viallet wrote:> Hi all, > > Supposing AVR is a configured as a Master SPI device. > Is it possible to discard AVR master SCK output signal and make SCK as an > input in order to apply external bitstream clock. > > My app is connecting a Quad voice A/MU law Codec (MSM7705) to an AVR SPI > bus. > > Many thanksProbably not -- why can't you configure the SPI port as a slave to get your job done? -- Tim Wescott Wescott Design Services http://www.wescottdesign.com
Reply by ●March 14, 20052005-03-14
Le Mon, 14 Mar 2005 09:07:59 -0800, Tim Wescott a �crit�:> habib bouaziz-viallet wrote: > >> Hi all, >> >> Supposing AVR is a configured as a Master SPI device. >> Is it possible to discard AVR master SCK output signal and make SCK as an >> input in order to apply external bitstream clock. >> >> My app is connecting a Quad voice A/MU law Codec (MSM7705) to an AVR SPI >> bus. >> >> Many thanks > > Probably not -- why can't you configure the SPI port as a slave to get > your job done?Hi Tim, Configuring SPI bus in slave mode may require one more signal to drive SS. AVR received and send at the same time DOUT and DIN to and from CoDeC. Master SPI does not require SS driven, IHMO Master mode should be more simple if fortunenately SCK would be a real clock input. Habib, betula.fr
Reply by ●March 14, 20052005-03-14
"habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message news:pan.2005.03.14.18.45.45.766538@mynewserverposfix.com...> Configuring SPI bus in slave mode may require one more signal to drive SS. > AVR received and send at the same time DOUT and DIN to and from CoDeC. > Master SPI does not require SS driven, IHMO Master mode should be more > simple if fortunenately SCK would be a real clock input.But, by being master, the SPI interface knows exactly when a byte starts, because the transmission is started when a byte is written in the data register. In slave mode, you only know the beginning of a byte by detecting the assertion of SS. In short: what you want is impossible. Meindert
Reply by ●March 14, 20052005-03-14
After reviewing: http://www2.okisemi.com/site/datasheets/msm7705-01-02-03.pdf?var_docid=msm7705-01-02-03&var_intro=Intro-3480 This can be done with a simple CPLD. ( did it once already, albet 2 years ago ) Make the AVR an SPI master, with the 7705 a slave. The CPLD will translate the RSYNC into a "start". Count 24 BCLK pulses into 3 SPI bytes. After the first SPI interrupt, wait for the other 2 bytes. No Problem. Meindert Sprang wrote:> "habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message > news:pan.2005.03.14.18.45.45.766538@mynewserverposfix.com... > >>Configuring SPI bus in slave mode may require one more signal to drive SS. >>AVR received and send at the same time DOUT and DIN to and from CoDeC. >>Master SPI does not require SS driven, IHMO Master mode should be more >>simple if fortunenately SCK would be a real clock input. > > > But, by being master, the SPI interface knows exactly when a byte starts, > because the transmission is started when a byte is written in the data > register. In slave mode, you only know the beginning of a byte by detecting > the assertion of SS. In short: what you want is impossible. > > Meindert > >
Reply by ●March 15, 20052005-03-15
Le Mon, 14 Mar 2005 20:21:22 +0100, Meindert Sprang a �crit�:> "habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message > news:pan.2005.03.14.18.45.45.766538@mynewserverposfix.com... >> Configuring SPI bus in slave mode may require one more signal to drive SS. >> AVR received and send at the same time DOUT and DIN to and from CoDeC. >> Master SPI does not require SS driven, IHMO Master mode should be more >> simple if fortunenately SCK would be a real clock input. > > But, by being master, the SPI interface knows exactly when a byte starts, > because the transmission is started when a byte is written in the data > register. In slave mode, you only know the beginning of a byte by detecting > the assertion of SS. In short: what you want is impossible. > > MeindertHi Meindert, Take a look at this : http://cjoint.com/?dpjsxvXDQV AVR is configured as a slave. SS is grounded, therefore AVR is not able to update SPI shift reg for transmit after a byte is completely received from CodeC. That's why i'm seeking about Master SPI mode with AVR. Believe me i'm not a flasher ! Habib betula.fr
Reply by ●March 15, 20052005-03-15
"habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message news:pan.2005.03.15.08.09.18.196326@mynewserverposfix.com...> Hi Meindert, > > Take a look at this : > http://cjoint.com/?dpjsxvXDQV > AVR is configured as a slave. SS is grounded, therefore AVR is not able to > update SPI shift reg for transmit after a byte is completely received > from CodeC. That's why i'm seeking about Master SPI mode with AVR.So your problem is SS stays low, you cannot access the shift register. Can't you connect SS to the same sync signal that you feed to RSYNC? Meindert
Reply by ●March 15, 20052005-03-15
Le Tue, 15 Mar 2005 09:42:52 +0100, Meindert Sprang a �crit�:> "habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message > news:pan.2005.03.15.08.09.18.196326@mynewserverposfix.com... >> Hi Meindert, >> >> Take a look at this : >> http://cjoint.com/?dpjsxvXDQV >> AVR is configured as a slave. SS is grounded, therefore AVR is not able to >> update SPI shift reg for transmit after a byte is completely received >> from CodeC. That's why i'm seeking about Master SPI mode with AVR. > > So your problem is SS stays low,Rrrrrriiiiiiiight ! you cannot access the shift register. Can't> you connect SS to the same sync signal that you feed to RSYNC?I cannot do that regarding FSYNC waveform. It seems that a little more complex signals generation circuitry must be implemented to drive SS properly. Many thanks, Habib betula.fr
Reply by ●March 15, 20052005-03-15
"habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message news:pan.2005.03.15.09.00.34.946375@mynewserverposfix.com...> > So your problem is SS stays low, > Rrrrrriiiiiiiight ! > you cannot access the shift register. Can't > > you connect SS to the same sync signal that you feed to RSYNC? > I cannot do that regarding FSYNC waveform. It seems that a little more > complex signals generation circuitry must be implemented to drive SS > properly.But if you would run the AVR as master and use the SS pin to drive RSYNC, it would work, right? The level on the SS pin must be controlled by your software anyway, so you can time it as you please. Meindert
Reply by ●March 15, 20052005-03-15
Le Tue, 15 Mar 2005 10:11:06 +0100, Meindert Sprang a �crit�:> "habib bouaziz-viallet" <habib@mynewserverposfix.com> wrote in message > news:pan.2005.03.15.09.00.34.946375@mynewserverposfix.com... >> > So your problem is SS stays low, >> Rrrrrriiiiiiiight ! >> you cannot access the shift register. Can't >> > you connect SS to the same sync signal that you feed to RSYNC? >> I cannot do that regarding FSYNC waveform. It seems that a little more >> complex signals generation circuitry must be implemented to drive SS >> properly. > > But if you would run the AVR as master and use the SS pin to drive RSYNC, it > would work, right? > The level on the SS pin must be controlled by your software anyway, so you > can time it as you please.SS controlled by soft, AVR as a Master ... it could work, but i will try to find out more about AVR Slave mode. In fact i'm not very inclined for the moment to cut PCB traces and so ... for implement AVR Master mode. For sure anyway it will work this very day. thanx, Habib betula.fr
