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Bit banging for 8051, SPI

Started by methi June 12, 2005
Hi Jim,

Whats happening is that its sending the right data for the first 16
clock cycles...

Then its not stopping...

It send all 0's


Again the right data...


So somehow the spi0dat reg is receiving the info repeatedly....

I have tried using delays between the bytes


I have also tried with just one byte for 8 clock cycles...


Same error...

It is due to SW....but i dont see wats wrong with the SW....


thanks,
Methi
Jim Granville wrote:
> methi wrote: > > Its 16 clock pulses > > > > > > Wrong data in the sense... > > > > Every alternate bit is reversed > > Wow - It is very hard to imagine a failure mode that would do that. > Check the device errata, but it would be _very_ hard to > do this by accident in silicon! > Suspect operator error - what patterns did you use ? > > > And it doesnt stop with 16 clock cycles.. > > > > > > It generates another 16 clock cycles with all logic '0's. > > anything inconsistent like this screams SW oops, not HW. > If you see correct length data, and clocks, that suggests the > port and SFR setups are OK, > > You should connect MOSI to MISO, and read back single bytes, with > a rolling test pattern. First use a SW delay to space the Bytes, then > use the SPIF or ==, and check it works the same. > > -jg
In article <1118553243.761323.196020@g43g2000cwa.googlegroups.com>,
methi <gmethi@gmail.com> wrote:
>Hi, >Does anybody have any idea about bit banging using SPI interface for >microcontrollers....esp the 8051...
Go to my page below. Select the subject "flash programming ..."
> >Thank you, >Methi >
-- -- Albert van der Horst,Oranjestr 8,3511 RA UTRECHT,THE NETHERLANDS Economic growth -- like all pyramid schemes -- ultimately falters. albert@spenarnc.xs4all.nl http://home.hccnet.nl/a.w.m.van.der.horst