I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). When I connect I channel from DAC to I & Q channel of ADC, I am seeing vastly different digital outputs on ADC (sampling three pins on oscilloscope). What might be the cause?
Why does two channels of ADC give different outputs?
Started by ●November 29, 2005
Reply by ●November 29, 20052005-11-29
I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). When I connect I channel from DAC to I & Q channel of ADC, I am seeing vastly different digital outputs on ADC (sampling three pins on oscilloscope). What might be the cause?
Reply by ●November 29, 20052005-11-29
"Jerry Avins" <jya@ieee.org> wrote in message news:zJudne6ssMf6SxbeRVn-vg@rcn.net...> Frank wrote: > > I am injecting the DAC output from TI DAC290x-EVM to ADC (AnalogAD9218).> > When I connect I channel from DAC to I & Q channel of ADC, I am seeing > > vastly > > different digital outputs on ADC (sampling three pins on oscilloscope).What> > might > > be the cause? > > Analog offset and gain difference is most likely. Nonlinearity is > possible. Could a hold capacitor be defective? > > Jerry > -- > Engineering is the art of making what you want from things you can get. > �����������������������������������������������������������������������OMG! There are 3 ADC boards in my lab, all of them had been badly tampered and the one I am using is the least tampered piece. Maybe I am really doomed. :-(
Reply by ●November 30, 20052005-11-30
"Frank" <Francis.invalid@hotmail.com> wrote in message news:438bd5a3$1@news.starhub.net.sg...> I am injecting the DAC output from TI DAC290x-EVM to ADC (Analog AD9218). > When I connect I channel from DAC to I & Q channel of ADC, I am seeing > vastly > different digital outputs on ADC (sampling three pins on oscilloscope).What> might > be the cause? > > >When using logic analyzer to sample ADC outputs, i am getting strange outputs. Right channel, bit 9,8,7,6 stick to 1, bit 0 stick to zero, while bits 5,4,3,2,1 varies during active, while sticking to 1 during idle mode. Left channel, bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle mode, bit 8,6,3,2 switches during active, stick to 0 during idle (I expect 9:2 of both channel to behave in this manner), bit 1:0 are switching during idle and active (noise during idle mode). I double checked my settings, but found nothing wrong. How can I proceed now?
Reply by ●November 30, 20052005-11-30
"Frank" <Francis.invalid@hotmail.com> wrote in message news:438d4a78$1@news.starhub.net.sg...> When using logic analyzer to sample ADC outputs, i am getting strange > outputs. > > Right channel, > bit 9,8,7,6 stick to 1, bit 0 stick to zero, while bits 5,4,3,2,1 varies > during active, while sticking to > 1 during idle mode. > > Left channel, > bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idlemode,> bit 8,6,3,2 switches during > active, stick to 0 during idle (I expect 9:2 of both channel to behave in > this manner), bit 1:0 are > switching during idle and active (noise during idle mode).Do you use any bus control signal (RD in combination with CE for the ADC for example) to trigger the logic analyser? If not, you are just measuring all bus activity, not just the output from the ADC. Meindert
Reply by ●November 30, 20052005-11-30
"Meindert Sprang" <mhsprang@NOcustomSPAMware.nl> wrote in message news:11oqj75td1vni04@corp.supernews.com...> "Frank" <Francis.invalid@hotmail.com> wrote in message > news:438d4a78$1@news.starhub.net.sg... > > When using logic analyzer to sample ADC outputs, i am getting strange > > outputs. > > > > Right channel, > > bit 9,8,7,6 stick to 1, bit 0 stick to zero, while bits 5,4,3,2,1 varies > > during active, while sticking to > > 1 during idle mode. > > > > Left channel, > > bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle > mode, > > bit 8,6,3,2 switches during > > active, stick to 0 during idle (I expect 9:2 of both channel to behavein> > this manner), bit 1:0 are > > switching during idle and active (noise during idle mode). > > Do you use any bus control signal (RD in combination with CE for the ADCfor> example) to trigger the logic analyser? If not, you are just measuringall> bus activity, not just the output from the ADC. > > Meindert > >In my digital side, I have a PHY_EN pin which is high when the digital circuit repetitively sends out same data, and the digital circuits work for 30us and idle for 10us. On logic analyzer, I set the LA to start filling in the internal memory (256K) once PHY_EN is high, thus I can capture 20 repetitions. I am sure the data capture is correct.
Reply by ●November 30, 20052005-11-30
"Frank" <Francis.invalid@hotmail.com> wrote in message news:438d4f5d$1@news.starhub.net.sg...> In my digital side, I have a PHY_EN pin which is high when the digital > circuit repetitively sends > out same data, and the digital circuits work for 30us and idle for 10us.On> logic analyzer, I set > the LA to start filling in the internal memory (256K) once PHY_EN is high, > thus I can capture > 20 repetitions. I am sure the data capture is correct.And I am not. this PHY_EN signal, what does it drive on the processor? I can imagine that it just signals the processor data is available and that consequently, the processor issues bus cycles (set an address or CE, activate RD, read data, deactivate Rd and CE) to read the data. This means that data on the bus during this 30us is not data from the ADC all the time. Only when the ADC is read during the bus read cycle, valid ADC data is readable on the bus. Meindert
Reply by ●November 30, 20052005-11-30
"Meindert Sprang" <mhsprang@NOcustomSPAMware.nl> wrote in message news:11oqpeup6ur1k50@corp.supernews.com...> "Frank" <Francis.invalid@hotmail.com> wrote in message > news:438d4f5d$1@news.starhub.net.sg... >> In my digital side, I have a PHY_EN pin which is high when the digital >> circuit repetitively sends >> out same data, and the digital circuits work for 30us and idle for 10us. > On >> logic analyzer, I set >> the LA to start filling in the internal memory (256K) once PHY_EN is >> high, >> thus I can capture >> 20 repetitions. I am sure the data capture is correct. > > And I am not. this PHY_EN signal, what does it drive on the processor? > I can imagine that it just signals the processor data is available and > that > consequently, the processor issues bus cycles (set an address or CE, > activate RD, read data, deactivate Rd and CE) to read the data. This means > that data on the bus during this 30us is not data from the ADC all the > time. > Only when the ADC is read during the bus read cycle, valid ADC data is > readable on the bus. > > Meindert > >Ah! I understand what you mean now. PHY_EN is a stable signal, while my clock period is 25ns, in each frame, digital side is sending some 1200 I/Q samples, one pair of samples each cycle and unchanged throughout the clock cycle. From the datasheet of ADC, I don't see there is any Rd or CD signal, it's as plain as ADC outputs are hold stable and change every 25ns. After all is done, I think I had better flag a "faulty ADC board" message to the up layer. since even when I disconnect ADC input, many of the pins mentioned below still to high level, sampled by a logic analyzer's 400MHz clock. Left channel, bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle mode, bit 8,6,3,2 switches during active, stick to 0 during idle (I expect 9:2 of both channel to behave in this manner), bit 1:0 are switching during idle and active (noise during idle mode).
Reply by ●November 30, 20052005-11-30
"Frank" <Frank@Frank.com> wrote in message news:dmk525$34f$1@reader01.singnet.com.sg...> Ah! I understand what you mean now. PHY_EN is a stable signal, while my > clock > period is 25ns, in each frame, digital side is sending some 1200 I/Q > samples, > one pair of samples each cycle and unchanged throughout the clock cycle. > > From the datasheet of ADC, I don't see there is any Rd or CD signal, it'sas> plain as ADC outputs are hold stable and change every 25ns.That is correct. The rising edge of ENCa and b (clock) sample the signal and on the falling edge, a valid word can be read from the databus. So your analyzer should trigger on the falling edge of the ENC signal Meindert
Reply by ●November 30, 20052005-11-30
Frank schrieb:> bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle mode, > bit 8,6,3,2 switches during > active, stick to 0 during idle (I expect 9:2 of both channel to behave in > this manner), bit 1:0 are > switching during idle and active (noise during idle mode). > > I double checked my settings, but found nothing wrong. How can I proceed > now?Forget the individual bits, look at the binary values in total! As I told you before, noise of an arbitrary low value can toggle all bits of the ADC. There is nothing wrong with that. If your voltage is just between 0 (0x000) and -1 (0x3FF) an error of -epsilon will result in an output of -1 and an error of +epsilon will result in an output of 0 for any epsilon greater 0. So, even if your noise level is one electron charge you can see flipping bits. Look at the binary values (all bits together!) and determine the magnitude of the noise. If it is 1 LSB, move on. Nothing to see here. If it is small, but greater than 1 LSB try to answer why you believe the analog noise on your board is smaller than what you see in your measurement. Kolja Sulimma
