Why does two channels of ADC give different outputs?

"Meindert Sprang" <mhsprang@NOcustomSPAMware.nl> wrote in message
news:11orioqaohu3v71@corp.supernews.com...
> "Frank" <Frank@Frank.com> wrote in message
> news:dmk525$34f$1@reader01.singnet.com.sg...
> > Ah! I understand what you mean now. PHY_EN is a stable signal, while my
> > clock
> > period is 25ns, in each frame, digital side is sending some 1200 I/Q
> > samples,
> > one pair of samples each cycle and unchanged throughout the clock cycle.
> >
> > From the datasheet of ADC, I don't see there is any Rd or CD signal,
it's
> as
> > plain as ADC outputs are hold stable and change every 25ns.
>
> That is correct. The rising edge of ENCa and b (clock) sample the signal
and
> on the falling edge, a valid word can be read from the databus. So your
> analyzer should trigger on the falling edge of the ENC signal
>
>
> Meindert
>
>

I was aware of this, however now I am asynchronously sampling at 400MHz,
thus
I am expecting each I/Q sample to be stable and correct for at least 22.5ns
assuming
the LA has miscaptured for one 2.5ns cycle.

"Frank" <Francis.invalid@hotmail.com> wrote in message
news:438e8b5d$1@news.starhub.net.sg...
> I was aware of this, however now I am asynchronously sampling at 400MHz,
> thus
> I am expecting each I/Q sample to be stable and correct for at least
22.5ns
> assuming
> the LA has miscaptured for one 2.5ns cycle.

Are you saying that within one ENC cycle, the data is not stable around the
falling clock edge?

Meindert

"Frank" <Frank@Frank.com> wrote in message
news:dmk525$34f$1@reader01.singnet.com.sg...
>
> "Meindert Sprang" <mhsprang@NOcustomSPAMware.nl> wrote in message
> news:11oqpeup6ur1k50@corp.supernews.com...
> > "Frank" <Francis.invalid@hotmail.com> wrote in message
> > news:438d4f5d$1@news.starhub.net.sg...
> >> In my digital side, I have a PHY_EN pin which is high when the digital
> >> circuit repetitively sends
> >> out same data, and the digital circuits work for 30us and idle for
10us.
> > On
> >> logic analyzer, I set
> >> the LA to start filling in the internal memory (256K) once PHY_EN is
> >> high,
> >> thus I can capture
> >> 20 repetitions. I am sure the data capture is correct.
> >
> > And I am not. this PHY_EN signal, what does it drive on the processor?
> > I can imagine that it just signals the processor data is available and
> > that
> > consequently, the processor issues bus cycles (set an address or CE,
> > activate RD, read data, deactivate Rd and CE) to read the data. This
means
> > that data on the bus during this 30us is not data from the ADC all the
> > time.
> > Only when the ADC is read during the bus read cycle, valid ADC data is
> > readable on the bus.
> >
> > Meindert
> >
> >
>
> Ah! I understand what you mean now. PHY_EN is a stable signal, while my
> clock
> period is 25ns, in each frame, digital side is sending some 1200 I/Q
> samples,
> one pair of samples each cycle and unchanged throughout the clock cycle.
>
> From the datasheet of ADC, I don't see there is any Rd or CD signal, it's
as
> plain as ADC outputs are hold stable and change every 25ns.
>
> After all is done, I think I had better flag a "faulty ADC board" message
to
> the up layer. since even when I disconnect ADC input, many of the pins
> mentioned
> below still to high level, sampled by a logic analyzer's 400MHz clock.
>
> Left channel,
> bit 7,5 stick to 0, bit 9,4 switches during active, stick to 1 in idle
mode,
> bit 8,6,3,2 switches during
> active, stick to 0 during idle (I expect 9:2 of both channel to behave in
> this manner), bit 1:0 are
> switching during idle and active (noise during idle mode).
>
>
>

Sigh! What should I say!!! After working a number of times, I realized that
the
god damned LA strobes are broken, and managed to sort out the broken ones
with an everchanging pin. With this discovery, I think I will get on much
easier.