Hi All, I have a FPGA system which requres better than 1pSec jitter. When I ask the Xtal MFG they advise there are 2 methods of measuring Jitter Peak to Peak and an averaging method Measuring the same Xtal the result can be significatly differment values between the 2 methods. Does any one have any information on the 2 methods (or more) how to measure jitter. What would FPGA input expect? Regards JG
1pSec Jitter
Started by ●January 14, 2006
Reply by ●January 14, 20062006-01-14
Joe G (Home) wrote:> Hi All, > > I have a FPGA system which requres better than 1pSec jitter. > > When I ask the Xtal MFG they advise there are 2 methods of measuring Jitter > Peak to Peak and an averaging method > > Measuring the same Xtal the result can be significatly differment values > between the 2 methods. > > Does any one have any information on the 2 methods (or more) how to measure > jitter. > > What would FPGA input expect? > > Regards > JG > >What do you mean by 1 psec jitter? Do you mean Rj, Dj, Tj? Are you measuring Time Interval error, cycle-to-cycle, or something else? I would recommend doing some reading. You can start at http://www.agilent.com/find/jitter Scroll down to "Key Library Information" and download (and read) all of the White Papers and Application notes. One of the first things you'll find is that it's probably impossible to measure 1psec of jitter. As with any other measurement, there is the concept of the smallest measureable unit. In the jitter world, this is the Jitter Measurement Floor, and typical values are 80 fsec to 2 psec. I personally can't imagine anything going on in an FPGA that would be affected by 1 psec of jitter. More info would be advisable. GS
Reply by ●January 14, 20062006-01-14
Sorry, The Osc driving the FPGA calls for 1pSec jitter. I am just trying to understand the 2 methods and how they relate to FPGA requirements. JG "Joe G (Home)" <joe.g@optusnet.com.au> wrote in message news:43c8ea45$0$11844$afc38c87@news.optusnet.com.au...> Hi All, > > I have a FPGA system which requres better than 1pSec jitter. > > When I ask the Xtal MFG they advise there are 2 methods of measuring > Jitter Peak to Peak and an averaging method > > Measuring the same Xtal the result can be significatly differment values > between the 2 methods. > > Does any one have any information on the 2 methods (or more) how to > measure jitter. > > What would FPGA input expect? > > Regards > JG > >
Reply by ●January 14, 20062006-01-14
On Sat, 14 Jan 2006 23:10:55 +1100, "Joe G \(Home\)" <joe.g@optusnet.com.au> wrote:>Hi All, > >I have a FPGA system which requres better than 1pSec jitter. > >When I ask the Xtal MFG they advise there are 2 methods of measuring Jitter >Peak to Peak and an averaging method > >Measuring the same Xtal the result can be significatly differment values >between the 2 methods. > >Does any one have any information on the 2 methods (or more) how to measure >jitter. > >What would FPGA input expect? > >Regards >JG >The only meaningful way to measure jitter is RMS. And even then, you have to specify the time interval over which it's to be measured. Peak-peak is poorly defined, but figure it's roughly 5 times RMS. In the telecom biz, any time variances measured within 0.1 second or less is "jitter", and above that it's "wander." A normal sampling scope measures one or at most a few periods of the input signal, which is "short-term" or "single period" jitter. 1 ps jitter is hard to measure. There are crystal oscillators that can do less than 1 ps. By the time you pass it through an FPGA, expect the result to be 10's of ps, maybe more. Why do you need 1 ps jitter? John
Reply by ●January 14, 20062006-01-14
Gob Stopper wrote:> Joe G (Home) wrote: >> >> I have a FPGA system which requres better than 1pSec jitter. >>... snip ...>> >> Does any one have any information on the 2 methods (or more) >> how to measure jitter. >... snip ...> > One of the first things you'll find is that it's probably > impossible to measure 1psec of jitter. As with any other > measurement, there is the concept of the smallest measureable > unit. In the jitter world, this is the Jitter Measurement Floor, > and typical values are 80 fsec to 2 psec.Circa 1970 I built a system for transmitting voice band, which was basically pulse duration modulated. The start was controlled by a separate clock. IIRC signal/noise measurements on the results indicated less that 1psec short term jitter. My memory seems to specify a pulse width in the range 0.25 to 1.25 uSec at about 12 Khz repetition rate, and a s/n ratio of better than 90 db. We were only interested in the noise level in the telephone audio band, roughly 300 hz to 3600 hz. We traded off repetition rate to simplify (and cheapen) equalization and aliasing filters, and met all signal quality objectives. -- "If you want to post a followup via groups.google.com, don't use the broken "Reply" link at the bottom of the article. Click on "show options" at the top of the article, then click on the "Reply" at the bottom of the article headers." - Keith Thompson More details at: <http://cfaj.freeshell.org/google/>
Reply by ●January 14, 20062006-01-14
"Joe G (Home)" wrote:> > Sorry, > > The Osc driving the FPGA calls for 1pSec jitter.The oscillator calls for? I thought this was a requirement from the FPGA. Do you mean that the FPGA calls for an oscillator jitter not to exceed 1 ps? What is the frequency? Is the FPGA running a PLL based on the oscillator? Basically, what fundamentally is setting the jitter requirement and why? -- Thad
Reply by ●January 14, 20062006-01-14
John Larkin wrote:> On Sat, 14 Jan 2006 23:10:55 +1100, "Joe G \(Home\)" > <joe.g@optusnet.com.au> wrote: > > >Hi All, > > > >I have a FPGA system which requres better than 1pSec jitter. > > > >When I ask the Xtal MFG they advise there are 2 methods of measuring Jitter > >Peak to Peak and an averaging method > > > >Measuring the same Xtal the result can be significatly differment values > >between the 2 methods. > > > >Does any one have any information on the 2 methods (or more) how to measure > >jitter. > > > >What would FPGA input expect? > > > >Regards > >JG > > > > The only meaningful way to measure jitter is RMS. And even then, you > have to specify the time interval over which it's to be measured. > Peak-peak is poorly defined, but figure it's roughly 5 times RMS. > > In the telecom biz, any time variances measured within 0.1 second or > less is "jitter", and above that it's "wander." > > A normal sampling scope measures one or at most a few periods of the > input signal, which is "short-term" or "single period" jitter. > > 1 ps jitter is hard to measure. There are crystal oscillators that can > do less than 1 ps. By the time you pass it through an FPGA, expect the > result to be 10's of ps, maybe more. > > Why do you need 1 ps jitter?I'd put my money on the "idiot manager" option. Idiot systems engineers also exist - "we've got this circuit which introduces 99psec of jitter, and the error budget is 100psec, so the clock can't introduce more than 1psec of additional jitter". Then there is idiot sales/marketing person who tells you that he/she can sell hundreds of units if you can just break the second law of thermodynamics. -- Bill Sloman, Nijmegen
Reply by ●January 14, 20062006-01-14
Hello Joe,> I have a FPGA system which requres better than 1pSec jitter. >Pretty tough requirement. Do you want to build some kind of Doppler?> When I ask the Xtal MFG they advise there are 2 methods of measuring Jitter > Peak to Peak and an averaging method > > Measuring the same Xtal the result can be significatly differment values > between the 2 methods. > > Does any one have any information on the 2 methods (or more) how to measure > jitter. >Jitter is usually looked at via an eye diagram on a blazingly fast scope. The scope manufacturers have app notes about that. But since your xtal mfg told you about two methods why not ask them?> What would FPGA input expect? >Depends what that FPGA is and what you want to do with it. Regards, Joerg http://www.analogconsultants.com
Reply by ●January 15, 20062006-01-15
Joe G (Home) wrote:> Sorry,>> The Osc driving the FPGA calls for 1pSec jitter.Do you mean the application specifies an oscillator with <1pSec jitter?> > I am just trying to understand the 2 methods and how they relate to FPGA > requirements. > > JG > > > "Joe G (Home)" <joe.g@optusnet.com.au> wrote in message > news:43c8ea45$0$11844$afc38c87@news.optusnet.com.au... > > Hi All,> >> > I have a FPGA system which requres better than 1pSec jitter.Tight requirement. What is the specific application?> > > > When I ask the Xtal MFG they advise there are 2 methods of measuring > > Jitter Peak to Peak and an averaging method > > > > Measuring the same Xtal the result can be significatly differment values > > between the 2 methods. > > > > Does any one have any information on the 2 methods (or more) how to > > measure jitter.There are more than two methods for measuring jitter (depending on just what it is you are trying to measure). Frequency domain measurements are commonly used for Dj prediction (although different test equip. mfrs use different techniques). Time domain for cycle to cycle and random jitter. Long term drift (just what long term is depends on the system) may or may not be an issue - that (just like all the other jitter sources) is system dependent. Note that different mfrs equipment will give you different results - even a different set of probes will vary the measurement, particularly at the speed you seem to need.> > > > What would FPGA input expect?What FPGA? What application?> > > > Regards > > JG > > > >When testing high speed links I designed the physical layer for, (5Gb/s) we used Tektronix equipment. Based on what I saw, they had some of the best equipment. Look here http://www2.tek.com/cmswpt/tifinder.lotr?cn=oscilloscopes&lc=EN for some app notes. In our application, we had to worry more about cycle to cycle and short term peak / rms jitter, but without knowing more I can't say what your app would consider an issue. Cheers PeteS
Reply by ●January 16, 20062006-01-16
On 14 Jan 2006 18:34:13 -0800, bill.sloman@ieee.org wrote:>> >> Why do you need 1 ps jitter? > >I'd put my money on the "idiot manager" option. Idiot systems engineers >also exist - "we've got this circuit which introduces 99psec of jitter, >and the error budget is 100psec, so the clock can't introduce more than >1psec of additional jitter".Probably the same guy that was upgrading to a 32-bit CPU and needed a 32-bit ADC to match. John
