EmbeddedRelated.com
Forums
Memfault State of IoT Report

JTAG and flash

Started by Alice January 26, 2006
Alice

The JTAG spec does not define a connector pinout and everyone has done
it differently. In particular programming a PLD is done once and does
not require that much data and so the pinout that ALTERA hase chosen is
very simple. However an ARM debugger would be interacted with
constantly during software dev and might load several MBytes of code
into the ARM. It therefore wants the JTAG interface to run as fast as
possible and so the debugger manufacturer would choose a JTAG cable
appropriately.
It all comes down to whether the software can toggle TDI.TMS and CLK
and read TDO to get what it wants. Early debugger software could not
cope with anything else in the chain, more recent ones probably can but
when engineers are bitten once they never forget. The only advice you
will get is to use seperate chains. If the XSCALE and ARM rep say it
can be done then you need to see it before you believe them.

Colin

I accidentally deleted Tim's reply---but in response,

No, the Intel strata does not have a JTAG interface.To my knowledge (and 
I've searched diligently--although it was a few short months ago) no Flash 
mfr provides a JTAG interface. I'd love for someone here to prove me 
wrong....anyone?

Thanks,

Bo

"Bo" <bo@cephus.com> wrote in message 
news:7a04e$43d91854$18d6ec55$26466@KNOLOGY.NET...
> > "Alice" <ixqnxjpumxklao@mailinator.com> wrote in message > news:1138292638.466785.192420@g47g2000cwa.googlegroups.com... >> Thanks for the replies, I appologize about the flash error (instead of >> PLD). > > Alice, > > No need to apologize... perhaps my tone came across wrong... I was > expressing disappointment because a JTAG Flash IC would be really, really, > really cool. > > > >>I have another question. If I had an ARM chip and an xscale >> chip, and I connected TDI/TDO (and the other jtag pins) to the correct >> places on the ARM chip, would the same jtag cable/device work on the >> xscale chip if they were connected to the proper pins? I'm confused if >> each jtag cable/device is chip specific (is a jtag device used to >> communicate with an arm chip is different than one needed to >> communicate with an xscale chip?) > > No. You *can* chain all the JTAG devices together by chaining the TDO of > device #1 to the TDI of device #2, and so forth... BUT a word of caution. > I have been involved on several board integrations where devices from > various vendors did not 'play well' with each other. I'd recommend > separate chains for each mfr--if you have the real-estate/luxury of more > connectors and their costs. > > I also would run separate JTAG chains for any SoC design for the debug/ > internal microprocessor and the FPGA portion. > > Speaking from experience...although I know it is not *supposed* to cause > any problems. > > Paul >
Bo wrote:
> I accidentally deleted Tim's reply---but in response, > > No, the Intel strata does not have a JTAG interface.To my knowledge > (and I've searched diligently--although it was a few short months > ago) no Flash mfr provides a JTAG interface. I'd love for someone > here to prove me wrong....anyone? >
Oops. I beg your pardon. I think I had in mind the following paper which describes programming flash over JTAG. However, it uses the JTAG interface on a device connected to the flash (i.e. a CPU). Program Intel&#4294967295; Flash Memory Using the IEEE 1149.1 (JTAG) Test Access Port ftp://download.intel.com/design/flcomp/papers/30827401.pdf Surely this is just as useful though? When would you have flash that isn't connected to a CPU? You don't even have to download code to the CPU; you can simply hijack the CPU's pins (chip select, address and data bus) and do the flash programming from the host.
"Tim Clacy" <nospamtcl@nospamphaseone.nospamdk> wrote in message 
news:43da8636$0$38727$edfadb0f@dread12.news.tele.dk...
> Bo wrote: >> I accidentally deleted Tim's reply---but in response, >> >> No, the Intel strata does not have a JTAG interface.To my knowledge >> (and I've searched diligently--although it was a few short months >> ago) no Flash mfr provides a JTAG interface. I'd love for someone >> here to prove me wrong....anyone? >> > > Oops. I beg your pardon. I think I had in mind the following paper which > describes programming flash over JTAG. However, it uses the JTAG interface > on a device connected to the flash (i.e. a CPU). > > Program Intel&#4294967295; Flash Memory Using the IEEE 1149.1 (JTAG) Test Access Port > ftp://download.intel.com/design/flcomp/papers/30827401.pdf > > Surely this is just as useful though? When would you have flash that isn't > connected to a CPU?
Flash could easily be connected to a PLD or FPGA for use in signal generation for example.
>You don't even have to download code to the CPU; you can > simply hijack the CPU's pins (chip select, address and data bus) and do > the > flash programming from the host.
This doesn't sound too bad, but in the case where it's connected to a state-machine PLD or whatever, programming is still a royal pain. I encountered this on a Xilinx SoC design. Not exactly complicated, but sure did eat a lot of resources and time to get it working. Bo
On Fri, 27 Jan 2006 15:12:03 -0600, "Bo" <bo@cephus.com> wrote:

> >"Tim Clacy" <nospamtcl@nospamphaseone.nospamdk> wrote in message >news:43da8636$0$38727$edfadb0f@dread12.news.tele.dk... >> Bo wrote: >>> I accidentally deleted Tim's reply---but in response, >>> >>> No, the Intel strata does not have a JTAG interface.To my knowledge >>> (and I've searched diligently--although it was a few short months >>> ago) no Flash mfr provides a JTAG interface. I'd love for someone >>> here to prove me wrong....anyone? >>> >> >> Oops. I beg your pardon. I think I had in mind the following paper which >> describes programming flash over JTAG. However, it uses the JTAG interface >> on a device connected to the flash (i.e. a CPU). >> >> Program Intel&#4294967295; Flash Memory Using the IEEE 1149.1 (JTAG) Test Access Port >> ftp://download.intel.com/design/flcomp/papers/30827401.pdf >> >> Surely this is just as useful though? When would you have flash that isn't >> connected to a CPU? > >Flash could easily be connected to a PLD or FPGA for use in signal >generation for example. > >>You don't even have to download code to the CPU; you can >> simply hijack the CPU's pins (chip select, address and data bus) and do >> the >> flash programming from the host. > >This doesn't sound too bad, but in the case where it's connected to a >state-machine PLD or whatever, programming is still a royal pain. I >encountered this on a Xilinx SoC design. Not exactly complicated, but sure >did eat a lot of resources and time to get it working.
I agree, Using JTAG is an extremely simple in concept. The problem is one is shifting out 1000's of bits to perform a relative simple task such as a single bus read. The tools for debugging this is expensive or non existant. Only one bit may be incorrect, and the only result one see, is that it is not working. Finding the specific sequence which is not working is not neccessaraliy difficult --- just extremely time consuming. Coupled with this, the JTAG documentation on most parts are so sparse, that it borders on non existant. A standard layer on top of JTAG would make life much simpler. Unfortunately the chances of that seems to be very small. The only flash devices I know of that has a JTAG interface was the PLD+Flash devices made by waferscale. They were bought out I think by ST a number of years ago. IMO, One thing that would help with debugging such code would be an (open source) JTAG state machine simulator library that can simulate a JTAG state machine, together with various register sizes etc. It should have a well defined API, and a nice user interface that shows the current state of the JTAG state machine, and levels of the pins etc. driven by the JTAG chain. If one could use captured data from a JTAG chain as well as self generated data to drive such a simulator, it would help in reverse engineer the various debug protocols used on CPU cores, and not properly (or not at all) published by the manufacturers. Regards Anton Erasmus
Thanks, the replies have helped, but I still don't know which jtag
device to use.  I found a site where I can build my own arm9 jtag
adapter (http://jtag-arm9.sourceforge.net/hardware.html).  I see there
is software that comes with it, but it looks like it's only for the
ARM940 core.  What software would I need to use to get it to work with
the Altera PLD?  Am I correct in my assumption that the arm9 wiggler
would work if I have the right software and correctly connect the
adapter to the pins?

Alice wrote:
> Thanks, the replies have helped, but I still don't know which jtag > device to use. I found a site where I can build my own arm9 jtag > adapter (http://jtag-arm9.sourceforge.net/hardware.html). I see there > is software that comes with it, but it looks like it's only for the > ARM940 core. What software would I need to use to get it to work with > the Altera PLD? Am I correct in my assumption that the arm9 wiggler > would work if I have the right software and correctly connect the > adapter to the pins?
You have tried here ? http://www.altera.com/products/devkits/kit-cables.html -jg
Alice wrote:
> Thanks, the replies have helped, but I still don't know which jtag > device to use. I found a site where I can build my own arm9 jtag > adapter (http://jtag-arm9.sourceforge.net/hardware.html). I see there > is software that comes with it, but it looks like it's only for the > ARM940 core. What software would I need to use to get it to work with > the Altera PLD? Am I correct in my assumption that the arm9 wiggler > would work if I have the right software and correctly connect the > adapter to the pins? >
I think you need to understand JTAG better. The "wiggler" has no magic in it. Its just an interface to a serial chain of latchs and inputs. Decoding the serial data is where that magic is. So, yes the right software will do what you want. The other shoe is how fast the decoding is done be the software. The faster and more sophisticated the harware interface is, the easier for the software. Alteras website has free software for their PLDs. donald
On 31 Jan 2006 21:37:24 -0800, "Alice" <ixqnxjpumxklao@mailinator.com>
wrote:

>Thanks, the replies have helped, but I still don't know which jtag >device to use. I found a site where I can build my own arm9 jtag >adapter (http://jtag-arm9.sourceforge.net/hardware.html). I see there >is software that comes with it, but it looks like it's only for the >ARM940 core. What software would I need to use to get it to work with >the Altera PLD? Am I correct in my assumption that the arm9 wiggler >would work if I have the right software and correctly connect the >adapter to the pins?
Look on Altera's site. They have schematics for a simple parallel dongle, and software to program their PLDs. A slightly more generic programming software is a so called JAM player. Altera and many other companies provide the means of generating JAM files, which can then be used to program the specific device using the JAM Player. Regards Anton Erasmus
colin_toogood@yahoo.com wrote:
> Alice > > The JTAG spec does not define a connector pinout and everyone has done > it differently. In particular programming a PLD is done once and does > not require that much data and so the pinout that ALTERA hase chosen is > very simple. However an ARM debugger would be interacted with > constantly during software dev and might load several MBytes of code > into the ARM. It therefore wants the JTAG interface to run as fast as > possible and so the debugger manufacturer would choose a JTAG cable > appropriately. > It all comes down to whether the software can toggle TDI.TMS and CLK > and read TDO to get what it wants. Early debugger software could not > cope with anything else in the chain, more recent ones probably can but > when engineers are bitten once they never forget. The only advice you > will get is to use seperate chains. If the XSCALE and ARM rep say it > can be done then you need to see it before you believe them. > > Colin >
Checkout OpenOCD + Amontec JTAG Accelerator. OpenOCD is a stable JTAG server written in a very nice structure. (open source): - ARM7TDMI(-S) support - ARM720t support - ARM920t support - LPC2xxx flash support - CFI Flash support - a telnet interface (for low-level debugging tasks) - a GDB interface - support for Wiggler-style PC parallel port interfaces - support for FTDI FT2232C based devices - support for the Amontec Chameleon&#4294967295;s JTAG Accelerator configuration - ... http://openocd.berlios.de/web/ JTAG Accelerator help you to speed-up the JTAG interface from an EPP parallel port. The specification of the JTAG Accelerator is public. http://www.amontec.com Regards, Laurent

Memfault State of IoT Report