> Poor man's strobe, via the enable inputs of several HC688 decoders :-)))Do you have an AND gate anywhere in the path generating those enables? If so, make the gate 1 term wider and run the signal that makes the leading edge through a non-inverting buffer and into the and gate. That will delay the turn-on by a gate delay. (Stand on your head as required to get the polarities to work out right.) You probably can't prove no-contention by just reading the data sheets because the turn on/off specs cover voltage and temperature. But you might be able to convince yourself it will work OK after spending some time in the lab. -- These are my opinions, not necessarily my employer's. I hate spam.
74LVT transition times: How low can you go?
Started by ●February 28, 2007
Reply by ●March 3, 20072007-03-03
Reply by ●March 4, 20072007-03-04
Hal Murray wrote:>>Poor man's strobe, via the enable inputs of several HC688 decoders :-))) > > > Do you have an AND gate anywhere in the path generating those enables? >Only one AND chip and it's already fully occupied :-(> If so, make the gate 1 term wider and run the signal that makes > the leading edge through a non-inverting buffer and into the > and gate. That will delay the turn-on by a gate delay. > > (Stand on your head as required to get the polarities to work > out right.) > > You probably can't prove no-contention by just reading the data > sheets because the turn on/off specs cover voltage and temperature. > But you might be able to convince yourself it will work OK after > spending some time in the lab. >With the RC that has two time constants (and a Schmitt) it'll work fine. -- Regards, Joerg http://www.analogconsultants.com
Reply by ●March 4, 20072007-03-04
On Sun, 04 Mar 2007 21:52:33 GMT, Joerg <notthisjoergsch@removethispacbell.net> wrote:>Hal Murray wrote: > >>>Poor man's strobe, via the enable inputs of several HC688 decoders :-))) >> >> >> Do you have an AND gate anywhere in the path generating those enables? >> > >Only one AND chip and it's already fully occupied :-( > > >> If so, make the gate 1 term wider and run the signal that makes >> the leading edge through a non-inverting buffer and into the >> and gate. That will delay the turn-on by a gate delay. >> >> (Stand on your head as required to get the polarities to work >> out right.) >> >> You probably can't prove no-contention by just reading the data >> sheets because the turn on/off specs cover voltage and temperature. >> But you might be able to convince yourself it will work OK after >> spending some time in the lab. >> > >With the RC that has two time constants (and a Schmitt) it'll work fine.I just remembered this... http://analog-innovations.com/SED/CrudeDelay.pdf Lose the XOR for your purposes. This has delay plus snap action, so the edges don't get perverted like with typical RC delays. ...Jim Thompson -- | James E.Thompson, P.E. | mens | | Analog Innovations, Inc. | et | | Analog/Mixed-Signal ASIC's and Discrete Systems | manus | | Phoenix, Arizona Voice:(480)460-2350 | | | E-mail Address at Website Fax:(480)460-2142 | Brass Rat | | http://www.analog-innovations.com | 1962 | I love to cook with wine. Sometimes I even put it in the food.
Reply by ●March 6, 20072007-03-06
Jim Granville wrote:> CBFalconer wrote: >> Jim Granville wrote: >>> CBFalconer wrote: >>>> Jim Granville wrote: >>>> >>>>... snip ... >>>> >>>>> The other issue that can bite, is transistion oscillation. >>>>> Without a Schmitt, if you scoped the output at the 4mA peak, >>>>> you will see what I mean. That can cause real problems with >>>>> downstream devices - I've seen even unrelated pin drive have >>>>> edge-oscillation effects that needed external remedies. >>>> >>>> Actually a Schmidt trigger input can make things worse. Without >>>> it, a single CMOS inverter using a Vcc that allows a linear input >>>> bias can stabilize using just a large resistor from output to >>>> input. With it, the input voltage must be some sort of sawtooth, >>>> depending on the innate input capacitance. The half period will >>>> be the time needed for the input to rise (or fall) the hysteresis >>>> voltage. >>> >>> You've lost me here. I'm talking about unwanted transistion >>> oscillation, which can be in the 100's of MHz region in modern >>> devices. There is no feedback resistor, and a Schmitt IP does not >>> make transistion oscillation worse, it removes it. >>> >>> I think you are thinking of RC oscillators, or even Crystal >>> oscillators ( using unbuffered gates, HCU04 type) which are about >>> oscillators you'd try and do linear feedback, without real care. >> >> There is always feedback, possibly only via the capacitance between >> input and output. It is possible that the leakage current into the >> input pin is so small that the system becomes quiescent, but not >> too likely. That is why one normally ties unused inputs to ground >> (or Vcc). With, say 12V CMOS it is possible to bias the input pin >> so that both transistors are entirely off, and the system is >> stable. This is one of the curses of low Vcc CMOS logic - there is >> no real stable point where both input transistors are firmly off. > > You've moved even further from my transistion oscillation instance, > but I'm lost as to what "both transistors are entirely off" can > mean.I've been delaying a response, because I beieve somebody has their head up, and I have come to the conclusion that it is me. I was thinking of old fashioned 4000 series CMOS, where the transistors are enhancement mode, with thresholds of something like 8V. At a Vcc of 12 V no input voltage can turn both units on, but as you reduce Vcc you come to the condition where both are on at some input level. I really am not familiar with the characteristics of the devices forming modern chips, so my opinion becomes relatively worthless. -- <http://www.cs.auckland.ac.nz/~pgut001/pubs/vista_cost.txt> <http://www.securityfocus.com/columnists/423> "A man who is right every time is not likely to do very much." -- Francis Crick, co-discover of DNA "There is nothing more amazing than stupidity in action." -- Thomas Matthews
Reply by ●March 6, 20072007-03-06
CBFalconer wrote:> Jim Granville wrote: > >>CBFalconer wrote: >> >>>Jim Granville wrote: >>> >>>>CBFalconer wrote: >>>> >>>>>Jim Granville wrote: >>>>> >>>>>... snip ... >>>>> >>>>> >>>>>>The other issue that can bite, is transistion oscillation. >>>>>>Without a Schmitt, if you scoped the output at the 4mA peak, >>>>>>you will see what I mean. That can cause real problems with >>>>>>downstream devices - I've seen even unrelated pin drive have >>>>>>edge-oscillation effects that needed external remedies. >>>>> >>>>>Actually a Schmidt trigger input can make things worse. Without >>>>>it, a single CMOS inverter using a Vcc that allows a linear input >>>>>bias can stabilize using just a large resistor from output to >>>>>input. With it, the input voltage must be some sort of sawtooth, >>>>>depending on the innate input capacitance. The half period will >>>>>be the time needed for the input to rise (or fall) the hysteresis >>>>>voltage. >>>> >>>>You've lost me here. I'm talking about unwanted transistion >>>>oscillation, which can be in the 100's of MHz region in modern >>>>devices. There is no feedback resistor, and a Schmitt IP does not >>>>make transistion oscillation worse, it removes it. >>>> >>>>I think you are thinking of RC oscillators, or even Crystal >>>>oscillators ( using unbuffered gates, HCU04 type) which are about >>>>oscillators you'd try and do linear feedback, without real care. >>> >>>There is always feedback, possibly only via the capacitance between >>>input and output. It is possible that the leakage current into the >>>input pin is so small that the system becomes quiescent, but not >>>too likely. That is why one normally ties unused inputs to ground >>>(or Vcc). With, say 12V CMOS it is possible to bias the input pin >>>so that both transistors are entirely off, and the system is >>>stable. This is one of the curses of low Vcc CMOS logic - there is >>>no real stable point where both input transistors are firmly off. >> >>You've moved even further from my transistion oscillation instance, >>but I'm lost as to what "both transistors are entirely off" can >>mean. > > > I've been delaying a response, because I beieve somebody has their > head up, and I have come to the conclusion that it is me. I was > thinking of old fashioned 4000 series CMOS, where the transistors > are enhancement mode, with thresholds of something like 8V. At a > Vcc of 12 V no input voltage can turn both units on, but as you > reduce Vcc you come to the condition where both are on at some > input level. I really am not familiar with the characteristics of > the devices forming modern chips, so my opinion becomes relatively > worthless. >Threshold is much lower on CD4000 since you can operate them down to 5V VCC, some of them even at 3V although they become like molasses down there. The problem is the opposite. Many people including me use them for analog purposes on occasion. If you bias an inverter that isn't a Schmitt at VCC/2 or via a feedback resistor and then run it at 12-15V VCC you will get an incredible cross current, to the point where the chip gets way too hot. Down at 3-5V things are more manageable but you still have both devices partially on. Just try it out. You can make quite good amplifiers for next to nothing in cost. -- Regards, Joerg http://www.analogconsultants.com
Reply by ●March 6, 20072007-03-06
CBFalconer wrote:> I've been delaying a response, because I beieve somebody has their > head up, and I have come to the conclusion that it is me. I was > thinking of old fashioned 4000 series CMOS, where the transistors > are enhancement mode, with thresholds of something like 8V. At a > Vcc of 12 V no input voltage can turn both units on, but as you > reduce Vcc you come to the condition where both are on at some > input level. I really am not familiar with the characteristics of > the devices forming modern chips, so my opinion becomes relatively > worthless.8V thresholds would have to be before my time ? ;) For the 4000 series devices we use today, have a look at http://www.standardics.nxp.com/products/hef/pdf/hef4069ub.pdf In Fig 4., you'll see thresholds in the 1.5-1.75V region. HCMOS drops that to around 1V, and LVC drops that to around 0.6V On the CPLD (ATF1502BE) we measured, the thesholds were 0.63V for NFET ~1uA, and -0.57V for the PFET ~1uA -jg
Reply by ●March 6, 20072007-03-06
Joerg wrote:> Threshold is much lower on CD4000 since you can operate them down to 5V > VCC, some of them even at 3V although they become like molasses down there. > > The problem is the opposite. Many people including me use them for > analog purposes on occasion. If you bias an inverter that isn't a > Schmitt at VCC/2 or via a feedback resistor and then run it at 12-15V > VCC you will get an incredible cross current, to the point where the > chip gets way too hot. Down at 3-5V things are more manageable but you > still have both devices partially on. Just try it out. You can make > quite good amplifiers for next to nothing in cost.yup .. and if you current feed them (supply thru a largish resistor) you can make nice low power (single digit uA region) 32KHz oscillators, from HEF4069UB. -jg
Reply by ●March 6, 20072007-03-06
Jim Granville wrote:> CBFalconer wrote: > >> I've been delaying a response, because I beieve somebody has their >> head up, and I have come to the conclusion that it is me. I was >> thinking of old fashioned 4000 series CMOS, where the transistors >> are enhancement mode, with thresholds of something like 8V. At a >> Vcc of 12 V no input voltage can turn both units on, but as you >> reduce Vcc you come to the condition where both are on at some >> input level. I really am not familiar with the characteristics of >> the devices forming modern chips, so my opinion becomes relatively >> worthless. > > > 8V thresholds would have to be before my time ? ;) >Them's were the tube days. Of course, most of those are depletion mode devices. SCNR.> For the 4000 series devices we use today, have a look at > http://www.standardics.nxp.com/products/hef/pdf/hef4069ub.pdf > > > In Fig 4., you'll see thresholds in the 1.5-1.75V region. > HCMOS drops that to around 1V, and LVC drops that to > around 0.6V > > On the CPLD (ATF1502BE) we measured, the thesholds were > 0.63V for NFET ~1uA, and -0.57V for the PFET ~1uA >And the lower it goes the more leakage has to be dealt with. Probably Jim has pulled his hair at times about that. I couldn't because my hair is already gone :-( -- Regards, Joerg http://www.analogconsultants.com
Reply by ●March 6, 20072007-03-06
Joerg wrote:> Threshold is much lower on CD4000 since you can operate them down to 5V > VCC, some of them even at 3V although they become like molasses down there. > > The problem is the opposite. Many people including me use them for > analog purposes on occasion. If you bias an inverter that isn't a > Schmitt at VCC/2 or via a feedback resistor and then run it at 12-15V > VCC you will get an incredible cross current, to the point where the > chip gets way too hot. Down at 3-5V things are more manageable but you > still have both devices partially on. Just try it out. You can make > quite good amplifiers for next to nothing in cost.The schematic solutions using 40xx and 74xx as the analog parts were quite popular and even published in the textbooks about 30 years ago. It kind of worked, but it never worked for very good. The linearity and the gain is quite poor. Changing to different logic series required components change if it worked at all. The CMOS devices operating in the linear mode were quite easy to fall into the thyristor latchup. So I would not recommend using the tricks like that for production. Vladimir Vassilevsky DSP and Mixed Signal Design Consultant http://www.abvolt.com
Reply by ●March 6, 20072007-03-06
Vladimir Vassilevsky wrote:> > > Joerg wrote: > > >> Threshold is much lower on CD4000 since you can operate them down to >> 5V VCC, some of them even at 3V although they become like molasses >> down there. >> >> The problem is the opposite. Many people including me use them for >> analog purposes on occasion. If you bias an inverter that isn't a >> Schmitt at VCC/2 or via a feedback resistor and then run it at 12-15V >> VCC you will get an incredible cross current, to the point where the >> chip gets way too hot. Down at 3-5V things are more manageable but you >> still have both devices partially on. Just try it out. You can make >> quite good amplifiers for next to nothing in cost. > > > The schematic solutions using 40xx and 74xx as the analog parts were > quite popular and even published in the textbooks about 30 years ago. It > kind of worked, but it never worked for very good. The linearity and the > gain is quite poor. Changing to different logic series required > components change if it worked at all. The CMOS devices operating in the > linear mode were quite easy to fall into the thyristor latchup. So I > would not recommend using the tricks like that for production. >What many of those publications failed to mention is to take a very close look at the cross current specs (not all parts are spec'd for that) and set VCC accordingly. Or current limit/source the supply. Else, yes, it could go kablouie on you. There are several popular products that use this trick and were in production for many years, if not decades. One example is the Datong RF clipper. It's the blue box in the first picture: http://www.qsl.net/m0ezp/radio-datong.html I've got one. Stunning performance. -- Regards, Joerg http://www.analogconsultants.com
