Changing refresh rate for DRAM while in operation?

<sendthis@gmail.com> wrote in message 
news:1193382473.115596.137900@k79g2000hse.googlegroups.com...
>
>> Here is a free suggestion (the price is right):
>> I would write a specific word-pattern with an even mix of 1 and 0 into
>> every location in the whole DRAM.
>> Then read back sequentially at a slow pace through all addresses,
>> always checking the readback.
>> Sooner or later, you will pick up an error, becaue you exceeded the
>> refresh delay.
>> You may want to repeat this with different starting addresses and with
>> different word patterns.
>
> The problem is during the read (I'm assuming you mean by disabling the
> refresh altogether and relying solely on the refresh after read) is
> that it takes several seconds to read from the DRAM. This will always
> exceed the refresh time right? From the start_address to end_address
> it takes quite a while for a 64Mbit DRAM. The spec calls for a 64ms
> refresh.
>

A much bigger problem is that reading a DRAM location implicitly refreshes 
that entire row. Therefore, you can't poll to find out if your refresh is 
frequent enough because each read will perform a refresh.

You will probably find that if you disable refresh totally then most of the 
memory will stay intact for several seconds (and across power cycles!). If I 
was you, I would disable refresh totally, write a test pattern to memory and 
then check it after about five seconds to find one location that has failed. 
Once you've picked that one, use that as your test location. You can then 
write to it with various refresh rates and see if the data is still valid 
many seconds later. You probably won't have found the worst-case cell in the 
device, but that's rather academic because every device will be different 
anyway so this is far from a valid characterization test. 

On Oct 26, 3:07 am, sendt...@gmail.com wrote:
> > Here is a free suggestion (the price is right):
> > I would write a specific word-pattern with an even mix of 1 and 0 into
> > every location in the whole DRAM.
> > Then read back sequentially at a slow pace through all addresses,
> > always checking the readback.
> > Sooner or later, you will pick up an error, becaue you exceeded the
> > refresh delay.
> > You may want to repeat this with different starting addresses and with
> > different word patterns.
>
> The problem is during the read (I'm assuming you mean by disabling the
> refresh altogether and relying solely on the refresh after read) is
> that it takes several seconds to read from the DRAM. This will always
> exceed the refresh time right? From the start_address to end_address
> it takes quite a while for a 64Mbit DRAM. The spec calls for a 64ms
> refresh.


The other problem is that the act of reading in fact performs
a refresh so depending on the way you hooked up the address
lines, you may actually refresh the entire chip many times
over while reading through once.

But I think Peter's second statement is really important.  When
you think of the mechanism for a single-event upset, how much
difference is a fully charged capacitor vs a capacitor allowed
to drain for the specified 64mS (or some other refresh rate of
your choice).  If the standard refresh rate only allows a charge
drop of say 20%, I don't see how doubling the rate and allowing
a charge drop of only 10% will greatly reduce the percentage
of events that cannot discharge a given capacitor.  Under normal
operating conditions I would imagine that the charge drain is
much smaller than 20%.

In the old days, before the semiconductor manufacturers found
radiation being emitted by some of the early ceramic packages,
a lot of large memory systems used ECC with scrubbing refresh
to make the system at all usable.  In my opinion reducing the
likelihood of uncorrectable multiple events via scrubbing is
more effective than keeping your capacitors at peak charge.

Regards,
Gabor

On Mon, 22 Oct 2007 22:44:56 -0700, sendthis@gmail.com wrote:

>Hi,
>
>I'm trying to control a SDR SDRAM (Micron 64Mbit chip) using an Altera
>DE2 board. I've gotten the hardware interface squared away (thanks
>everyone for your help!).
>
>Now it's the tricky stuff. Any one have an idea how I can change the
>refresh rate while the RAM is in operation?

If you roll your own controller (easy enough for SDR SDRAM) or can
understand the core you are given, you can find what controls the
refresh rate; invariably a counter. 

Replace the counter with an absurdly long one (say 32 bits), whose count
length is controllable from a register accessible to whatever host CPU
(NIOS in this case). 

It's either a reloadable down counter, which reloads and generates a
refresh cycle when it hits zero; in which case you reload it from the
register; or an up-counter which refreshes and resets to zero when a
comparator triggers; in which case the register holds the comparator
value.

Then you have direct control of the refresh rate without messing with
clock frequencies etc.

- Brian

David Spencer wrote:
> 
... snip ...
> 
> A much bigger problem is that reading a DRAM location implicitly
> refreshes that entire row. Therefore, you can't poll to find out
> if your refresh is frequent enough because each read will perform
> a refresh.
> 
> You will probably find that if you disable refresh totally then
> most of the memory will stay intact for several seconds (and
> across power cycles!). If I was you, I would disable refresh
> totally, write a test pattern to memory and then check it after
> about five seconds to find one location that has failed. Once
> you've picked that one, use that as your test location. You can
> then write to it with various refresh rates and see if the data
> is still valid many seconds later. You probably won't have found
> the worst-case cell in the device, but that's rather academic
> because every device will be different anyway so this is far
> from a valid characterization test.

Things may be much 'worse' than that.  I remember one of the first
16k RAM chips developed, which we found (by accident) could retain
information for days with power off.  This couldn't be trusted. 
Those chips were actually static memory 2k x 8 bits, not dynamic.

-- 
 Chuck F (cbfalconer at maineline dot net)
   Available for consulting/temporary embedded and systems.
   <http://cbfalconer.home.att.net>



-- 
Posted via a free Usenet account from http://www.teranews.com

On Oct 26, 8:05 am, Gabor <ga...@alacron.com> wrote:
[]
>
> In the old days, before the semiconductor manufacturers found
> radiation being emitted by some of the early ceramic packages,
> a lot of large memory systems used ECC with scrubbing refresh
> to make the system at all usable.  In my opinion reducing the
> likelihood of uncorrectable multiple events via scrubbing is
> more effective than keeping your capacitors at peak charge.
>
> Regards,
> Gabor

I think you may be addressing his real problem as he mentions in
another post.


On Oct 25, 7:31 pm, sendt...@gmail.com wrote:
[]
> I do appreciate everyone's replies and I certainly didn't mean to
> ignore your answers and questions that were trying to help me.
>
> Paul mentioned in his reply that it makes sense to do it in different
> temperatures. This really is similar to what I am trying to do. I'm
> trying to figure out (partly) if the refresh rate will help with the
> radiation tolerance of the device (i.e. speeding it up).

I think your test is a difficult one since you are looking for
failures due to discharge by random radiation effects. Slowing down
the refresh and finding one or few cells that tend to discharge more
quickly than the rest as a few others have suggested does not really
apply to the problem.

You haven't specified what kind of radiation you are testing for (high
energy cosmic rays, background radiation, BETA radiation, Nuclear
power plant radiation(monitoring or robotic device?), or nuclear bomb)
This is not a simple test rig. The programming of the refresh rate is
a minor problem. The problem, if I understand your description
correctly, is
measure the failure rate DUE TO RADIATION versus refresh rate.
Since radiation induced failures are random, you'll have to do a good
number of test runs at various refresh rates to get a handle on the
range of failure rate (to be able to say
there were Y failures +/-y at refresh rate X) You need to be able to
sort out what failures are due to the memory device itself and what is
due to the radiation.

The supplier of your memory may be able to give some advice on this
test setup. (or are you working for the memory manufacturer?) I think
you do not need to change the refresh rate dynamically. You should be
able to do test runs at a fixed refresh rate, get the failure rate,
reboot with a new refresh rate and start again.  Depending on the
radiation source you may need to replace the memory modules in a
controlled way, to deal with the cases of permanent damage by the
radiation.

I'm not trying to be offensive with this final question/comment, but I
take it your background is computer science only, right? You may need
to get someone with a background in physical sciences (a physicist) to
help design the experiment.  (I have a BS in physics, but nuclear
physics is not one of my strong points.)

  HTH,
  Ed

<sendthis@gmail.com> wrote in message 
news:1193355065.572064.187420@y42g2000hsy.googlegroups.com...
>
>> Probably so, but it isn't at all obvious how to answer.  The DRAM
>> doesn't care as long as every row is refreshed within the specified
>> amount of time.  Some refresh all rows in a big burst, others one
>> at a time uniformly over the interval.  You can refresh faster than
>> the specified rate, but there is no system independent way to
>> describe how to do that.  For systems with a variable speed
>> clock (such as power saving modes) one does have to design
>> the refresh system appropriately.
>
> I know the mode register is initialized at the beginning with the
> refresh rate (and some other information). Is it possible to reload
> the mode register and will this do anything to the stored data (such
> as letting all the caps discharge)? Is this even possible?
>
> I do appreciate everyone's replies and I certainly didn't mean to
> ignore your answers and questions that were trying to help me.
>
>
> Paul mentioned in his reply that it makes sense to do it in different
> temperatures. This really is similar to what I am trying to do. I'm
> trying to figure out (partly) if the refresh rate will help with the
> radiation tolerance of the device (i.e. speeding it up).
>
Yes it will.  The charge in the cell decreases over time.  So running 
with a faster refresh rate will, at least somewhat, increase the minimum 
charge in a cell and increase the signal on the bit line.

Have you reviewed the literature on this?  I can't believe that this type 
of experiment hasn't already been done.

del
>
> 

On Oct 26, 8:09 am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Mon, 22 Oct 2007 22:44:56 -0700, sendt...@gmail.com wrote:
> >Hi,
>
> >I'm trying to control a SDR SDRAM (Micron 64Mbit chip) using an Altera
> >DE2 board. I've gotten the hardware interface squared away (thanks
> >everyone for your help!).
>
> >Now it's the tricky stuff. Any one have an idea how I can change the
> >refresh rate while the RAM is in operation?
>
> If you roll your own controller (easy enough for SDR SDRAM) or can
> understand the core you are given, you can find what controls the
> refresh rate; invariably a counter.
>
> Replace the counter with an absurdly long one (say 32 bits), whose count
> length is controllable from a register accessible to whatever host CPU
> (NIOS in this case).
>
> It's either a reloadable down counter, which reloads and generates a
> refresh cycle when it hits zero; in which case you reload it from the
> register; or an up-counter which refreshes and resets to zero when a
> comparator triggers; in which case the register holds the comparator
> value.
>
> Then you have direct control of the refresh rate without messing with
> clock frequencies etc.
>
> - Brian

If it is an up counter with a comparator, be careful: if it is an
equality rather than a greater-than comparator, and the CPU sets the
trigger value to less than the current value of the counter, then the
counter will have to roll all the way over, and likely miss a refresh,
with potential data loss resulting.

Andy

> I think your test is a difficult one since you are looking for
> failures due to discharge by random radiation effects. Slowing down
> the refresh and finding one or few cells that tend to discharge more
> quickly than the rest as a few others have suggested does not really
> apply to the problem.

No, I'm looking at the retention. How does radiation effect the
retention characteristics of the DRAM. As mentioned in another reply,
it makes sense to change DRAM refresh rates at different temperatures.
Does this help in a radiation environment?



>
> You haven't specified what kind of radiation you are testing for (high
> energy cosmic rays, background radiation, BETA radiation, Nuclear
> power plant radiation(monitoring or robotic device?), or nuclear bomb)
> This is not a simple test rig. The programming of the refresh rate is
> a minor problem. The problem, if I understand your description
> correctly, is

We are using gammas for this test. Following students will use other
radiation sources.

>
> The supplier of your memory may be able to give some advice on this
> test setup. (or are you working for the memory manufacturer?) I think
> you do not need to change the refresh rate dynamically. You should be
> able to do test runs at a fixed refresh rate, get the failure rate,
> reboot with a new refresh rate and start again.  Depending on the
> radiation source you may need to replace the memory modules in a
> controlled way, to deal with the cases of permanent damage by the
> radiation.

Not working for the mfg. I wish I was, then I'd have more resources.
I'm working for a university (as in, I'm a student).

>
> I'm not trying to be offensive with this final question/comment, but I
> take it your background is computer science only, right? You may need
> to get someone with a background in physical sciences (a physicist) to
> help design the experiment.  (I have a BS in physics, but nuclear
> physics is not one of my strong points.)
>

I have a nuclear engineer helping me with this. Actually, it's the
other way around since this isn't really related to the deliverables
for my thesis.

On Oct 26, 9:09 am, Brian Drummond <brian_drumm...@btconnect.com>
wrote:
> On Mon, 22 Oct 2007 22:44:56 -0700, sendt...@gmail.com wrote:
> >Hi,
>
> >I'm trying to control a SDR SDRAM (Micron 64Mbit chip) using an Altera
> >DE2 board. I've gotten the hardware interface squared away (thanks
> >everyone for your help!).
>
> >Now it's the tricky stuff. Any one have an idea how I can change the
> >refresh rate while the RAM is in operation?
>
> If you roll your own controller (easy enough for SDR SDRAM) or can
> understand the core you are given, you can find what controls the
> refresh rate; invariably a counter.
>
> Replace the counter with an absurdly long one (say 32 bits), whose count
> length is controllable from a register accessible to whatever host CPU
> (NIOS in this case).
>
> It's either a reloadable down counter, which reloads and generates a
> refresh cycle when it hits zero; in which case you reload it from the
> register; or an up-counter which refreshes and resets to zero when a
> comparator triggers; in which case the register holds the comparator
> value.
>
> Then you have direct control of the refresh rate without messing with
> clock frequencies etc.
>
> - Brian

Actually that sounds like a good idea. I'll look into that, thanks.

-Eric

On Fri, 26 Oct 2007 07:35:32 -0700, Andy <jonesandy@comcast.net> wrote:

>On Oct 26, 8:09 am, Brian Drummond <brian_drumm...@btconnect.com>
>wrote:

>> Replace the counter with an absurdly long one (say 32 bits), whose count
>> length is controllable from a register accessible to whatever host CPU
>> (NIOS in this case).

>If it is an up counter with a comparator, be careful: if it is an
>equality rather than a greater-than comparator, and the CPU sets the
>trigger value to less than the current value of the counter, then the
>counter will have to roll all the way over, and likely miss a refresh,
>with potential data loss resulting.

Good point: if doing that, it's advisable to reset the counter (and
issue a refresh) whenever you set the trigger value.

- Brian