I2C trick?

Vladimir Vassilevsky wrote:
> "Stefan Reuther" <stefan.news@arcor.de> wrote in message
>>If I see that correctly, the line-swapped device will see a start
>>condition whenever the master sends a '1' bit followed by a '0'; it will
>>see a '0' bit during a direction swap (between master releasing SDA
>>after the last bit and slave pulling SDA for acknowledge), and a '1' bit
>>during inactive periods (between a stop condition and a start
>>condition). This means, it is possible to construct a valid transaction
>>that is seen as, say, a start condition plus 8 data bits by the
>>line-swapped device. That device may now start pulling its SDA (i.e. the
>>current SCL) to low as an acknowledge, and thus lock up the bus.
> 
> I thought for a little about what you suggested, still I can't see how this
> is possible. Would you please give an example.

Here's the example I sketched on an envelope yesterday. Disclaimer: I'm
currently at home with no embedded stuff around me, if I made a mistake,
please correct me. For brevity, I assume only 4 bits per byte.

"~" High, "_" Low, "|" Spike caused by direction change. Use fixed-width
font.
                                                  v
SCL  ~~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~\_/~

SDA  ~\_____/~~~~~~~\___|___|_______________|___|__________

Seen by addressed device:
      S   0   1   1   0   A   0   0   0   0   A   0   0   0

Seen by line-swapped device:
                    S   0   0               0   0

At this point, a hypothetical line-swapped device with address "0000"
would be addressed and pull its SDA (=current SCL) low to acknowledge.
The SCL edge marked "v" and all following ones would therefore not
happen, the bus being locked up now.

I'm not sure whether it's possible to construct a sequence where the
line-swapped device sees a nonzero address, though. Maybe you're
"rescued" by the observation that every "1" bit on the "correct" bus is
seen as a stop condition by the line-swapped device, and *should* reset
its I2C receiver.


  Stefan