> Alas, the only fairly complete clone was not been
optimized very much (~ 50 MHz in a Cyclone 1C20). How does Plasma compare to
> that?
>
Plasma was about 40 MHz in a Cyclone 1C12. However, the main issue
was the not very well designed memory interface. And the core
had no caches at all! That's a performance killer for a pipelined
RISC.
> I later understood an alternative to stalling for
interdependencies: late detect and "lazy" flushing. The experimental prototype
> based on this was completely dominated by the ALU, seeing 90 - 130 MHz (1C20)
depending on how many stages I used for the ALU.
> IIRC, the rest of the pipe was about 6 stages. I'd love to complete this
to the point where it can boot Linux, but I have other
> priorities today.
ok, cool - that's the frequency range of the NISO.
> Ah, but doesn't LEON include a complete MMU?
Even without it, I think it is much much larger than my clone, MB, and Nios
II.
Yes, it's larger: about 8000 LCs compared to the 2000 LCs of a NIOS.
Martin
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Microblaze In FPGA Virtex4 ML401?
Started by ●July 20, 2007
Reply by ●July 26, 20072007-07-26
Reply by ●July 26, 20072007-07-26
[Appologies if the formatting is missing or screwed up. Yahoo! Mail
doessn't like me much.]
Martin Schoeberl wrote:Plasma was about 40 MHz in a Cyclone 1C12. However, the main issue
was the not very well designed memory interface. And the core
had no caches at all! That's a performance killer for a pipelined
RISC.
An instruction cache is definitely a must (all my clones have one), but it isn't trivial to make it such that it isn't tailor made for a particularly FPGA.
The memory interface has caused me lots of grief. We went over some of this when we discussed alternatives to Wishbone but didn't come to much of a conclusion. The ideal pipe between the memory controller and the caches looks very different from what you need for other peripherals. Did LEON have a good solution here?
I'll post my ALU in a different thread.
Cheers,
Tommy
---------------------------------
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Martin Schoeberl wrote:Plasma was about 40 MHz in a Cyclone 1C12. However, the main issue
was the not very well designed memory interface. And the core
had no caches at all! That's a performance killer for a pipelined
RISC.
An instruction cache is definitely a must (all my clones have one), but it isn't trivial to make it such that it isn't tailor made for a particularly FPGA.
The memory interface has caused me lots of grief. We went over some of this when we discussed alternatives to Wishbone but didn't come to much of a conclusion. The ideal pipe between the memory controller and the caches looks very different from what you need for other peripherals. Did LEON have a good solution here?
I'll post my ALU in a different thread.
Cheers,
Tommy
---------------------------------
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Reply by ●July 27, 20072007-07-27
> An instruction cache is definitely a must (all my
clones have one), but it isn't trivial to make it such that it isn't
tailor made
> for a particularly FPGA.
yes, that's true. I have vendor specific files for this.
>
> The memory interface has caused me lots of grief. We went over some of this when we discussed alternatives to Wishbone but didn't
> come to much of a conclusion. The ideal pipe between the memory controller and the caches looks very different from what you need
> for other peripherals. Did LEON have a good solution here?
Again agree. Wishbone has a combinatorial path from the master
request to the slave ack which makes it very hard to place
registers for address and data at the FPGA pins (using some
pipelining for the memory interface). First I added another
signal to the WB. Later I decided to roll my own interconnection
interface, which I called SimpCon:
http://www.opencores.org/projects.cgi/web/simpcon/overview
LEON uses the AMBA bus.
Martin
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> for a particularly FPGA.
yes, that's true. I have vendor specific files for this.
>
> The memory interface has caused me lots of grief. We went over some of this when we discussed alternatives to Wishbone but didn't
> come to much of a conclusion. The ideal pipe between the memory controller and the caches looks very different from what you need
> for other peripherals. Did LEON have a good solution here?
Again agree. Wishbone has a combinatorial path from the master
request to the slave ack which makes it very hard to place
registers for address and data at the FPGA pins (using some
pipelining for the memory interface). First I added another
signal to the WB. Later I decided to roll my own interconnection
interface, which I called SimpCon:
http://www.opencores.org/projects.cgi/web/simpcon/overview
LEON uses the AMBA bus.
Martin
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
Reply by ●August 22, 20072007-08-22
Following up to my own posting is bad style, sorry, but I had to correct the
Fmax ...
Tommy Thorn wrote: Martin Schoeberl wrote:You did *a few* MIPS clones? I would be interested in that clones.
I've tried the Plasma, but was not very happy with it.
What in particular?
Alas, the only fairly complete clone was not been optimized very much (~ 50 MHz in a Cyclone 1C20). How does Plasma compare to that?
I dug it out again and either my memory was bad or Quartus has improved. A complete (but unoptimized) system with UART, 640x480x1 video and other stuff takes 9,294 LE (46 %) and clocks in at 70 MHz in a EP1C20-C7. Knowing how much there is that could be improved with a completely rewritten pipeline, I wonder what the performance could ultimately be. BTW it does have a 16 KiB I$, but no D$.
Tommy
---------------------------------
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Tommy Thorn wrote: Martin Schoeberl wrote:You did *a few* MIPS clones? I would be interested in that clones.
I've tried the Plasma, but was not very happy with it.
What in particular?
Alas, the only fairly complete clone was not been optimized very much (~ 50 MHz in a Cyclone 1C20). How does Plasma compare to that?
I dug it out again and either my memory was bad or Quartus has improved. A complete (but unoptimized) system with UART, 640x480x1 video and other stuff takes 9,294 LE (46 %) and clocks in at 70 MHz in a EP1C20-C7. Knowing how much there is that could be improved with a completely rewritten pipeline, I wonder what the performance could ultimately be. BTW it does have a 16 KiB I$, but no D$.
Tommy
---------------------------------
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Yahoo! Small Business gives you all the tools to get online.
