POP-11 (PDP-11/40 in an FPGA)

Richard wrote:
> I think that is best. Since I can't find any decent hardware
> reference manuals,

The only excuse for not finding hardware reference manuals is not
looking for them!

The PDP-11/34 is a fairly representative midrange PDP-11 model, with
about the same capabilities as the 11/40 but slightly more modern
implementation. I think it's a better reference for how a PDP-11
is designed than the 11/40. The maintenance manual has lots of theory
of operation:
http://bitsavers.org/pdf/dec/pdp11/1134/KD11EA_CPU_Maint.pdf

The schematics are here:
http://bitsavers.org/pdf/dec/pdp11/1134/MP00190_1134A_KD11-EA.pdf

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--- In f..., "Eric Smith" wrote:
> The only excuse for not finding hardware reference manuals is not
> looking for them!

Hallo Eric,
sorry you missed the opportunity, and directed him to also look at
discussions of microprogrammed and bit slice versions of the PDP11 ;-)

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--- In f..., woodelf wrote:
>
> rtstofer wrote:
>
> > I have already recoded the ALU. The propogation delay is horrible -
> > on the order of 33 nS or so. I'm going to take another look at it.
> > The Xilinx synthesizer is creating 26 logic levels! This is because
> > there isn't a clear MUX, just a lot of somewhat random logic.
>
> How is the carry in the alu factored? If it is configured as default
> with ripply carry 26 levels sounds right since 16 levels are used
> for the carry. That leaves 10 levels for simple logic. Ben.
> PS. Still fast compared to the orginal machine.

In the POP-11 project, the author hand coded 16 bit wide
carry-lookahead adders. Certainly, Xilinx has a macro for such an
adder and I would be inclined to use it EXCEPT there are some oddities
in the overflow signal on the POP-11 that I couldn't convince myself
were met by the macro.

In looking at the RTL schematic, the problem comes up when various bit
patterns need to be stuffed in the condition codes. Instead of doing
this in some random way, a MUX would be cleaner and, hopefully, use a
fewer logic levels.

Richard

>

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--- In f..., "Eric Smith" wrote:
>
> Richard wrote:
> > I think that is best. Since I can't find any decent hardware
> > reference manuals,
>
> The only excuse for not finding hardware reference manuals is not
> looking for them!
>
> The PDP-11/34 is a fairly representative midrange PDP-11 model, with
> about the same capabilities as the 11/40 but slightly more modern
> implementation. I think it's a better reference for how a PDP-11
> is designed than the 11/40. The maintenance manual has lots of theory
> of operation:
> http://bitsavers.org/pdf/dec/pdp11/1134/KD11EA_CPU_Maint.pdf
>
> The schematics are here:
> http://bitsavers.org/pdf/dec/pdp11/1134/MP00190_1134A_KD11-EA.pdf
Thanks for the links! As I pointed out a while back, I know exactly
NOTHING about PDP-11's. I might have walked past a room that had one
but that's as close as I ever got.

I spent quite a bit of time wandering through Google looking for stuff
specifically related to the 11/40 and I didn't really come up with
anything better than the PDP-11/40 Processor Handbook and I think I
got that at bitsavers.org. I have it printed out and have used it
extensively while revisiting the ALU.

Logic drawings will be interesting!

In the end, the only goal is to get Unix V6 running. Just because...
I don't have any long time love affair with PDP's. That level of
commitment is reserved for the IBM 1130.

Richard

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rtstofer wrote:

> In the end, the only goal is to get Unix V6 running. Just because...
> I don't have any long time love affair with PDP's. That level of
> commitment is reserved for the IBM 1130.

Then why are you *NOT* doing that in a FPGA?

> Richard
Ben.
PS. Ok the hard drive, line printer and punch card
card reader/punch don't fit in one.Other than I/O
the IBM-1130 had a nice instruction set considering
the time era it was in.

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--- In f..., woodelf wrote:
>
> rtstofer wrote:
>
> > In the end, the only goal is to get Unix V6 running. Just because...
> > I don't have any long time love affair with PDP's. That level of
> > commitment is reserved for the IBM 1130.
>
> Then why are you *NOT* doing that in a FPGA?
>
> > Richard
> Ben.
> PS. Ok the hard drive, line printer and punch card
> card reader/punch don't fit in one.Other than I/O
> the IBM-1130 had a nice instruction set considering
> the time era it was in.
>

But, I already have... The FPGA implementation runs the entire IBM
software suite include DMS, Fortran, Macro Assembler, etc. Even
Robert Louden's "Three Dimension Tic-Tac-Toe" is running.

In the beginning I used a 25x80 VGA display core for the console
printer, a PS/2 keyboard core for the console keyboard and a pair of
serial port cores for the reader and printer.

I got lazy and loaded the OS on a 16Mb flash EEPROM and copied it to
RAM for a ram disk. That limited the system to 16k words versus a max
of 32k. I have started working on an IDE interface for one or more CF
drives. I have always viewed that as a 'someday' project because
source code was never stored on the disk. Building programs from
source decks is more interesting to watch if the disk is 'fresh'.

It's been running for several months and I will do a "show and tell"
at the Vintage Computer Fair, Nov 3rd, at the Computer Museum in
Mountain View. There's a 5th annual IBM 1130 party at the fair.

For that evolution, the console display and keyboard will be replaced
with yet another serial port so that there will be 3 instances of
Hyperterminal running on a laptop (ugly...). Portability drives the
change.

I like the IO system: it is all based on DMA and if you want to add a
gadget, just hook it up to the DMA channel, invent an XIO command
sequence and write the driver. I only implemented the devices that
used DMA like the 2501 card reader and 1403 printer. I added delays
so that the IO devices run in real time.

The IBM 1130 is the first computer I ever used, starting in 1969.
There are a few 'firsts' in life that are worth remembering; this is
one. Fortunately, there were others...

Richard

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e2kspu wrote:
> sorry you missed the opportunity, and directed him to also look at
> discussions of microprogrammed and bit slice versions of the PDP11 ;-)

All commercial PDP-11 implementations have been microprogrammed other
than the original 11/20 (and the 11/15 OEM version). None used a
bit-slice CPU, though several used Am2901 bit slices in their FPPs.

CMU designed a bit slice processor compatible with the PDP-11, but
AFAIK the design is not published.

I've done some work toward reimplementing the J11 in an FPGA. The
J11 design uses a very large PLA, which takes a long time to P&R, and
the result requires a very large number of LUTs.

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--- In f..., "Eric Smith" wrote:
>
> e2kspu wrote:
> > sorry you missed the opportunity, and directed him to also look at
> > discussions of microprogrammed and bit slice versions of the PDP11 ;-)
>
> All commercial PDP-11 implementations have been microprogrammed other
> than the original 11/20 (and the 11/15 OEM version). None used a
> bit-slice CPU, though several used Am2901 bit slices in their FPPs.
>
> CMU designed a bit slice processor compatible with the PDP-11, but
> AFAIK the design is not published.

There is a chapter in G.Bells Book about it, and I remember seeing a
good description of it somewhere.

And, DEC liked the 2901 on a lot of occasions, FPUs etc.

> I've done some work toward reimplementing the J11 in an FPGA. The
> J11 design uses a very large PLA, which takes a long time to P&R, and
> the result requires a very large number of LUTs.

Interesting, I didn't see this problems ...

Anyway, I guess it was my personal joke. You didn't notice that your
message was number "2901" in this group ;-)

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--- In f..., "e2kcpu" wrote:
>
> --- In f..., "Eric Smith" wrote:
> > The only excuse for not finding hardware reference manuals is not
> > looking for them!
>
> Hallo Eric,
> sorry you missed the opportunity, and directed him to also look at
> discussions of microprogrammed and bit slice versions of the PDP11 ;-)
>

I'm open to bit-slice designs particularly if the microcode is
available. I took a class on 2901 design some time back in the
mid '80s but the class project was an 8086.

MANY years ago (like prior to the Altair 8800 in 1975) I designed the
CPU for the IBM 1130 using fusible link PROMS to hold the microcode and
the 74181 arithmetic chips (with the look-ahead chip). Unfortunately,
RAM was still a price issue in '75 and when the Altair hit the streets,
I abandoned the 1130.

Thirty years later it fits on a board the size of a postcard...

But, sure, if there are bit-slice projects around, I would certainly
consider porting them to an FPGA.

The goal remains unchanged: get Unix V6 to boot. Then hang a couple of
additional drives on the controller so I can add the source files and
recompile the OS. Oh, and the additional drives can be images on a
larger drive. It's not like RK05's held very much data!

Richard

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> I like CPLD's for random logic. Other than RISC designs
> what little I done with the FPGA I was using ( and CPLD's)
> is routing kills you for all but the simplest designs.
> Ben.
>

That's certainly true! For my PDP11/40 ALU the timings are:

Total 38.663ns (17.120ns logic, 21.543ns route) (44.3% logic, 55.7% route)

4.9 nS of the route is the OBUF on the assumed output pins and
excluding it leaves the timing at 34.17 ns with about 50% logic and
50% route. The OBUF time will disappear when the ALU is integrated
into the data path.

I probably can't do a lot about the route delay so even if I cut the
logic delay in half, it would only make a 25% improvement.

Maybe I should just leave it alone and hope that it works!

Richard

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