> Most projects implemented in Spartan 3 will have good
use for
> the block RAM within the projects themselves. So I don't think
> it's a good idea to reserve all of the RAM for the analyzer.
>
> Hellwig
>
Almost certainly true! However, for the POP-11 project, I haven't
seen much need for BlockRAM. In looking at the code, as given, I
don't see any internal RAM used other than what might be allocated
during synthesis.
Richard
POP-11 (PDP-11/40 in an FPGA)
Started by ●August 16, 2007
Reply by ●September 7, 20072007-09-07
Reply by ●September 7, 20072007-09-07
> I once wrote such a program as part of a project in
which
> I created my own hardware description language (named SHLD,
> "simple hardware description language") and a simulator for
> it. I wanted to display its output nicely and so wrote a
> converter from the output of my simulator to VCD format.
> You can grab the whole project from here:
> http://homepages.fh-giessen.de/~hg53/shdl
> The converter can be found in subdirectory vcd.
Looking at the SFL code for the POP-11/40 project, I have to say that
the SFL language is the most descriptive I have ever seen. It is
certainly a 'high level' approach to hardware description, far removed
from RTL.
What I'm not as keen on is the fact that the translation to VHDL
creates a lot of subexpressions which get 'v_netxxx' (or similar)
names. It is sometimes difficult to figure out just what is happening.
I started looking at the idea of taking the translated VHDL and
recoding it so that I can understand what is going on. I have made
some progress (the top module and the ALU) but I am beginning to think
it is a fools' exercise. If I could really understand SFL, what
difference does it make if the VHDL is a little obscure?
The POP-11 is still a backburner project. I have purchased a few used
books re: the PDP-11 but it will be a while before I get deeply involved.
Richard
> I created my own hardware description language (named SHLD,
> "simple hardware description language") and a simulator for
> it. I wanted to display its output nicely and so wrote a
> converter from the output of my simulator to VCD format.
> You can grab the whole project from here:
> http://homepages.fh-giessen.de/~hg53/shdl
> The converter can be found in subdirectory vcd.
Looking at the SFL code for the POP-11/40 project, I have to say that
the SFL language is the most descriptive I have ever seen. It is
certainly a 'high level' approach to hardware description, far removed
from RTL.
What I'm not as keen on is the fact that the translation to VHDL
creates a lot of subexpressions which get 'v_netxxx' (or similar)
names. It is sometimes difficult to figure out just what is happening.
I started looking at the idea of taking the translated VHDL and
recoding it so that I can understand what is going on. I have made
some progress (the top module and the ALU) but I am beginning to think
it is a fools' exercise. If I could really understand SFL, what
difference does it make if the VHDL is a little obscure?
The POP-11 is still a backburner project. I have purchased a few used
books re: the PDP-11 but it will be a while before I get deeply involved.
Richard
Reply by ●September 22, 20072007-09-22
Chuck wrote:
> There are copyrights on the MICROCODE which was the basis for most if
> not all of the LSI-11 variants of the machine. Those copyrights are
> still valid (75 years post partum)
Are you sure the microcode is copyrighted? In the US, works created before
March 1, 1989 (effective date of the Berne Convention Implementation Act
of 1988, U.S. Public Law 100-568) had to bear a copyright notice in order
to be copyrighted. See 17 U.S.C. 405(a).
There are limited exceptions that allowed the owner of a work to correct
an accidental omission of the copyright notice, but I don't think DEC
PDP-11 microcode qualifies under any of these exceptions.
There is also a way for a copyright that was "lost" under the Berne
Convention Implementation Act to be restored under certain conditions
(Uruguay Round Agreements Act of 1994, U.S. Public Law 103-465), but
I don't think the PDP-11 microcode qualifies under that exception either.
Eric
> There are copyrights on the MICROCODE which was the basis for most if
> not all of the LSI-11 variants of the machine. Those copyrights are
> still valid (75 years post partum)
Are you sure the microcode is copyrighted? In the US, works created before
March 1, 1989 (effective date of the Berne Convention Implementation Act
of 1988, U.S. Public Law 100-568) had to bear a copyright notice in order
to be copyrighted. See 17 U.S.C. 405(a).
There are limited exceptions that allowed the owner of a work to correct
an accidental omission of the copyright notice, but I don't think DEC
PDP-11 microcode qualifies under any of these exceptions.
There is also a way for a copyright that was "lost" under the Berne
Convention Implementation Act to be restored under certain conditions
(Uruguay Round Agreements Act of 1994, U.S. Public Law 103-465), but
I don't think the PDP-11 microcode qualifies under that exception either.
Eric
Reply by ●September 23, 20072007-09-23
Ok a couple of questions. I am not sure if this list is dead or not
but I'll see if I can add to the discussion.
The PDP 11 patents that DEC held are all expired (20 years) the last
one I believe expired in 2003 for some sort of PDP-11/70 MMU thing.
There are copyrights on the MICROCODE which was the basis for most if
not all of the LSI-11 variants of the machine. Those copyrights are
still valid (75 years post partum) but you can write your own
microcode and not worry too much. There is a company (whose name
escapes me) which used to make a pretty penny selling FPGA based
PDP-11s that ran faster than DEC ones and they were pretty aggressive
at pursuing people back in the 90's. Don't know if they are now or not.
Lastly the Altera DE2 board was clearly designed by someone who
thought building a PDP-11 was a cool idea since there are 18 switches,
LEDs and lots of peripherals on that board. And a decent sized FPGA. I
would expect you could boot RSX-11M, RT-11, Unix V7, or even RSTS/E on
that board while mimic'ing RL02's using FLASH ;-).
PLEASE PLEASE PLEASE post any VHDL you develop. The CPU test code
diagnostics are all available on line if you look around for the paper
tape images.
--Chuck
but I'll see if I can add to the discussion.
The PDP 11 patents that DEC held are all expired (20 years) the last
one I believe expired in 2003 for some sort of PDP-11/70 MMU thing.
There are copyrights on the MICROCODE which was the basis for most if
not all of the LSI-11 variants of the machine. Those copyrights are
still valid (75 years post partum) but you can write your own
microcode and not worry too much. There is a company (whose name
escapes me) which used to make a pretty penny selling FPGA based
PDP-11s that ran faster than DEC ones and they were pretty aggressive
at pursuing people back in the 90's. Don't know if they are now or not.
Lastly the Altera DE2 board was clearly designed by someone who
thought building a PDP-11 was a cool idea since there are 18 switches,
LEDs and lots of peripherals on that board. And a decent sized FPGA. I
would expect you could boot RSX-11M, RT-11, Unix V7, or even RSTS/E on
that board while mimic'ing RL02's using FLASH ;-).
PLEASE PLEASE PLEASE post any VHDL you develop. The CPU test code
diagnostics are all available on line if you look around for the paper
tape images.
--Chuck
Reply by ●September 25, 20072007-09-25
Hi Chuck,
On Wed, 2007-09-19 at 06:56 +0000, Chuck McManis wrote:
> Ok a couple of questions. I am not sure if this list is dead or not
> but I'll see if I can add to the discussion.
the list is certainly not dead... ;-)
This particular thread was continued in private mail - we
doubted that anybody on the list was interested in a highly
specialized technical discussion. But we can of course continue
it here if there is interest.
> PLEASE PLEASE PLEASE post any VHDL you develop. The CPU test code
> diagnostics are all available on line if you look around for the paper
> tape images.
Do you have any pointers? I found
http://www.parse.com/~museum/pdp11/software/index.html
but I think there must be more, perhaps on bitsavers.
Hellwig
On Wed, 2007-09-19 at 06:56 +0000, Chuck McManis wrote:
> Ok a couple of questions. I am not sure if this list is dead or not
> but I'll see if I can add to the discussion.
the list is certainly not dead... ;-)
This particular thread was continued in private mail - we
doubted that anybody on the list was interested in a highly
specialized technical discussion. But we can of course continue
it here if there is interest.
> PLEASE PLEASE PLEASE post any VHDL you develop. The CPU test code
> diagnostics are all available on line if you look around for the paper
> tape images.
Do you have any pointers? I found
http://www.parse.com/~museum/pdp11/software/index.html
but I think there must be more, perhaps on bitsavers.
Hellwig
Reply by ●September 28, 20072007-09-28
On Thu, 27 Sep 2007 14:57:11 -0000, e2kcpu wrote:
>> This particular thread was continued in private mail - we
>> doubted that anybody on the list was interested in a highly
>> specialized technical discussion. But we can of course continue
>> it here if there is interest.
>
>Just continue here, as this list is not really busy, or high traffic ;-)
>And there are few people lurking on this list who know the pdp's
>pretty well ...
I'd agree, assuming those writing actively don't mind.
Jon
To post a message, send it to: f...
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>> This particular thread was continued in private mail - we
>> doubted that anybody on the list was interested in a highly
>> specialized technical discussion. But we can of course continue
>> it here if there is interest.
>
>Just continue here, as this list is not really busy, or high traffic ;-)
>And there are few people lurking on this list who know the pdp's
>pretty well ...
I'd agree, assuming those writing actively don't mind.
Jon
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
Reply by ●September 29, 20072007-09-29
> This particular thread was continued in private mail
- we
> doubted that anybody on the list was interested in a highly
> specialized technical discussion. But we can of course continue
> it here if there is interest.
Just continue here, as this list is not really busy, or high traffic ;-)
And there are few people lurking on this list who know the pdp's
pretty well ...
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
> doubted that anybody on the list was interested in a highly
> specialized technical discussion. But we can of course continue
> it here if there is interest.
Just continue here, as this list is not really busy, or high traffic ;-)
And there are few people lurking on this list who know the pdp's
pretty well ...
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
Reply by ●October 10, 20072007-10-10
I am finally starting to work on this project. I used the sfl tools
to convert the sfl code to VHDL using the -split option. Now I am
looking at cleaning up the code.
In the segment_reg code, the converted VHDL has almost 700 lines of
code to implement two sets (kernel/user) of Page Address Registers and
Page Descriptor Registers.
Is there any reason I can't just declare a two-dimensional array of
std_logic_vectors? I'm thinking of something like:
entity segment_reg is port(
p_reset : in std_logic;
m_clock : in std_logic;
PDRout : out std_logic_vector(10 downto 0);
PARout : out std_logic_vector(11 downto 0);
PDRin : in std_logic_vector(10 downto 0);
PARin : in std_logic_vector(11 downto 0);
page : in std_logic_vector(2 downto 0);
mode : in std_logic;
writePDR : in std_logic;
writePAR : in std_logic;
seg_read : in std_logic);
end segment_reg;
architecture RTL of segment_reg is
type PAR_type is array (1 downto 0, 7 downto 0) of std_logic_vector(11
downto 0);
signal PARs : PAR_type := (others => (others => (others => '0')));
type PDR_type is array (1 downto 0, 7 downto 0) of std_logic_vector(10
downto 0);
signal PDRs : PDR_type := (others => (others => (others => '0')));
begin
process(m_clock, p_reset, mode, page)
begin
if m_clock'event and m_clock = '1' then
if p_reset = '1' then
PDRs <= (others => (others => (others => '0')));
PARs <= (others => (others => (others => '0')));
else
if writePDR = '1' then
PDRs(CONV_INTEGER(mode), CONV_INTEGER(page)) <= PDRin;
end if;
if writePAR = '1' then
PARs(CONV_INTEGER(mode), CONV_INTEGER(page)) <= PARin;
end if;
end if;
end if;
end process;
PDRout <= PDRs(CONV_INTEGER(mode), CONV_INTEGER(page)) when seg_read = '1'
else (others => '0');
PARout <= PARs(CONV_INTEGER(mode), CONV_INTEGER(page)) when seg_read = '1'
else (others => '0');
end RTL;
The WebPACK_ISE tools will compile the code and implement the design.
I was just wondering if I have made a huge error in simplifying the code.
Richard
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
to convert the sfl code to VHDL using the -split option. Now I am
looking at cleaning up the code.
In the segment_reg code, the converted VHDL has almost 700 lines of
code to implement two sets (kernel/user) of Page Address Registers and
Page Descriptor Registers.
Is there any reason I can't just declare a two-dimensional array of
std_logic_vectors? I'm thinking of something like:
entity segment_reg is port(
p_reset : in std_logic;
m_clock : in std_logic;
PDRout : out std_logic_vector(10 downto 0);
PARout : out std_logic_vector(11 downto 0);
PDRin : in std_logic_vector(10 downto 0);
PARin : in std_logic_vector(11 downto 0);
page : in std_logic_vector(2 downto 0);
mode : in std_logic;
writePDR : in std_logic;
writePAR : in std_logic;
seg_read : in std_logic);
end segment_reg;
architecture RTL of segment_reg is
type PAR_type is array (1 downto 0, 7 downto 0) of std_logic_vector(11
downto 0);
signal PARs : PAR_type := (others => (others => (others => '0')));
type PDR_type is array (1 downto 0, 7 downto 0) of std_logic_vector(10
downto 0);
signal PDRs : PDR_type := (others => (others => (others => '0')));
begin
process(m_clock, p_reset, mode, page)
begin
if m_clock'event and m_clock = '1' then
if p_reset = '1' then
PDRs <= (others => (others => (others => '0')));
PARs <= (others => (others => (others => '0')));
else
if writePDR = '1' then
PDRs(CONV_INTEGER(mode), CONV_INTEGER(page)) <= PDRin;
end if;
if writePAR = '1' then
PARs(CONV_INTEGER(mode), CONV_INTEGER(page)) <= PARin;
end if;
end if;
end if;
end process;
PDRout <= PDRs(CONV_INTEGER(mode), CONV_INTEGER(page)) when seg_read = '1'
else (others => '0');
PARout <= PARs(CONV_INTEGER(mode), CONV_INTEGER(page)) when seg_read = '1'
else (others => '0');
end RTL;
The WebPACK_ISE tools will compile the code and implement the design.
I was just wondering if I have made a huge error in simplifying the code.
Richard
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
Reply by ●October 14, 20072007-10-14
--- In f..., "rtstofer" wrote:
>
> I am finally starting to work on this project. I used the sfl tools
> to convert the sfl code to VHDL using the -split option. Now I am
> looking at cleaning up the code.
I'm not sure that the best way to start ;-)
I would start from scratch.
> In the segment_reg code, the converted VHDL has almost 700 lines of
> code to implement two sets (kernel/user) of Page Address Registers and
> Page Descriptor Registers.
>
> Is there any reason I can't just declare a two-dimensional array of
> std_logic_vectors? I'm thinking of something like:
Normally, you could use a two-dimensional array for this.
> The WebPACK_ISE tools will compile the code and implement the design.
Which FPGA ? Could you post P&R reports ?
> I was just wondering if I have made a huge error in simplifying the
code.
do you have a good testbench ?
Cheers
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
>
> I am finally starting to work on this project. I used the sfl tools
> to convert the sfl code to VHDL using the -split option. Now I am
> looking at cleaning up the code.
I'm not sure that the best way to start ;-)
I would start from scratch.
> In the segment_reg code, the converted VHDL has almost 700 lines of
> code to implement two sets (kernel/user) of Page Address Registers and
> Page Descriptor Registers.
>
> Is there any reason I can't just declare a two-dimensional array of
> std_logic_vectors? I'm thinking of something like:
Normally, you could use a two-dimensional array for this.
> The WebPACK_ISE tools will compile the code and implement the design.
Which FPGA ? Could you post P&R reports ?
> I was just wondering if I have made a huge error in simplifying the
code.
do you have a good testbench ?
Cheers
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
Reply by ●October 16, 20072007-10-16
> I'm not sure that the best way to start ;-)
> I would start from scratch.
I think that is best. Since I can't find any decent hardware
reference manuals, I will probably use the SFL code as background
information.
>
> Which FPGA ? Could you post P&R reports ?
I will be using the Spartan 3 Starter Board
http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD&Nav1=Products&Nav2=Programmable
because it has the required memory and I already have three of them.
And it uses SRAM so I don't have to mess around with the interface.
I have already recoded the ALU. The propogation delay is horrible -
on the order of 33 nS or so. I'm going to take another look at it.
The Xilinx synthesizer is creating 26 logic levels! This is because
there isn't a clear MUX, just a lot of somewhat random logic.
I'm not sure I like decoding the Op Code into MANY discrete signals.
It precludes the use of case statements and conditional assignment
isn't helping the number of logic levels.
I haven't looked at the possibility of microcoding the ALU but it is
on my list of possible approaches. The microcode word, selected from
the Op Code, could contain all of the fields necessary to drive MUX
select signals. I'll have to see how that works out.
> do you have a good testbench ?
I don't have any test capability at all. If it isn't included in the
WebPACK ISE, I don't have it. I do have a logic analyzer so there is
a certain amount of hope.
I had the identical problem on my prior project in that, until I tried
to bring up the OS, I didn't really know if the CPU worked. And there
were issues...
At the moment, I am revisiting a prior project so I can put on a
presentation at a Vintage Computer Festival. I'll get back to this in
early November.
Once I get clear on the MMU and how instruction fetch and operand
fetch work, the rest of the project should be straightforward.
I did notice that the POP-11 project doesn't include the definition
for the boot prom. There is an assembly language boot loader but
there is no place to put the machine code. I worked through the
details and added a 16W x 16bit ROM using the address and control
signals already provided. I think the ROM was removed because it was
part of the Parthenon library.
Richard
To post a message, send it to: f...
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> I would start from scratch.
I think that is best. Since I can't find any decent hardware
reference manuals, I will probably use the SFL code as background
information.
>
> Which FPGA ? Could you post P&R reports ?
I will be using the Spartan 3 Starter Board
http://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD&Nav1=Products&Nav2=Programmable
because it has the required memory and I already have three of them.
And it uses SRAM so I don't have to mess around with the interface.
I have already recoded the ALU. The propogation delay is horrible -
on the order of 33 nS or so. I'm going to take another look at it.
The Xilinx synthesizer is creating 26 logic levels! This is because
there isn't a clear MUX, just a lot of somewhat random logic.
I'm not sure I like decoding the Op Code into MANY discrete signals.
It precludes the use of case statements and conditional assignment
isn't helping the number of logic levels.
I haven't looked at the possibility of microcoding the ALU but it is
on my list of possible approaches. The microcode word, selected from
the Op Code, could contain all of the fields necessary to drive MUX
select signals. I'll have to see how that works out.
> do you have a good testbench ?
I don't have any test capability at all. If it isn't included in the
WebPACK ISE, I don't have it. I do have a logic analyzer so there is
a certain amount of hope.
I had the identical problem on my prior project in that, until I tried
to bring up the OS, I didn't really know if the CPU worked. And there
were issues...
At the moment, I am revisiting a prior project so I can put on a
presentation at a Vintage Computer Festival. I'll get back to this in
early November.
Once I get clear on the MMU and how instruction fetch and operand
fetch work, the rest of the project should be straightforward.
I did notice that the POP-11 project doesn't include the definition
for the boot prom. There is an assembly language boot loader but
there is no place to put the machine code. I worked through the
details and added a 16W x 16bit ROM using the address and control
signals already provided. I think the ROM was removed because it was
part of the Parthenon library.
Richard
To post a message, send it to: f...
To unsubscribe, send a blank message to: f...
