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I am supporting a design that utilizes the AD converter.
The AD reference voltage in this design can be varied from 0.4 V to 4.0 V changing the sensitivity range. The AD input voltage can be as high as 11V. I don't see a maximum input voltage spec on the AD inputs?? The maximum ratings lists "Input Voltage Vin 0.3 to +7.0" In my experience, I believe it is not advisable to overdrive the analog to digital converter greater than VCC (in this case 5V) or latch up can occur. Please advise. Janet Lefko Electrical Engineer Tekscan, Inc. 617 464-4500 x235 |
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Analog to Digital Converter Inputs
Started by ●January 19, 2004
Reply by ●January 19, 20042004-01-19
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At 01:34 PM 19/01/04 -0500, you wrote: > >I don't see a maximum input voltage spec on the AD inputs?? The maximum >ratings lists "Input Voltage Vin 0.3 to +7.0" > The electrical model for the A/D converter shows a ~20V zener at the input. I thought it was higher than that but can't find the reference to it. Regards John Samperi ****************************************************** Ampertronics Pty. Ltd. 11 Brokenwood Place Baulkham Hills, NSW 2153 AUSTRALIA Tel. (02) 9674-6495 Fax (02) 9674-8745 Email: Website http://ampertronics.com.au * Electronic Design * Technical Services * Contract Assembly ****************************************************** |
Reply by ●January 19, 20042004-01-19
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Janet: > The AD reference voltage in this design can be varied from 0.4 V > to 4.0 V changing the sensitivity range. I don't believe the HC11 will work with this range. In the electrical spex, there is a <VR, which is minimum differential between VRH and VRL, and it is specified as 3V. It says performance is verified down to 2.5v differential, but accuracy is not guaranteed at this level. > The AD input voltage can be as high as 11V. I don't think this is the case, either. For the converter to work, Vin must be less than VRH. In my experience, the chip will latch up if the A/D input is greater than VDD. It will destroy the input unless you have sufficient current limiting for the input (series resistor). > I don't see a maximum input voltage spec on the AD inputs?? The > maximum ratings lists "Input Voltage Vin 0.3 to +7.0" This is Absolute Maximum rating, ie the chip can be exposed to this voltage momentarily without damage. (Don't ask for a definition of "momentarily"). Continuous operation at this voltage will surely degrade the chip's performance permanently. > In my experience, I believe it is not advisable to overdrive the > analog to digital converter greater than VCC (in this case 5V) or > latch up can occur. Wise not to do so. Regards, Darrell Norquay Datalog Technology Inc. Calgary, Alberta, Canada Voice: (403) 243-2220 Fax: (403) 243-2872 Email: Web: www.datalog.ab.ca |
Reply by ●January 20, 20042004-01-20
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Janet Lefko wrote: [...] > I don't see a maximum input voltage spec on the AD inputs?? The > maximum ratings lists "Input Voltage Vin 0.3 to +7.0" because higher voltage will stress the gate oxide. > In my experience, I believe it is not advisable to overdrive the > analog to digital converter greater than VCC (in this case 5V) or > latch up can occur. no, the HC11 does not latch up. Believe the specs, it works. Oliver -- Oliver Betz, Muenchen |
Reply by ●January 20, 20042004-01-20
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Hello everyone, The maximum voltage that you can put on the A/D inputs is Vdd + 0.3 volts and even that isn't a good idea. You won't do any damage to the part but any leakage is going to affect the A/D conversion. So, from a practical standpoint, you should limit the A/D input voltage to be between Ground and Vdd. Now, that is the actual Vdd that you are putting on the part. So, if you are putting 4.8 volts on Vdd, then limit the A/D input to 4.8 volts. If you are putting 5.1 volts on Vdd, then you can put 5.1 volts on an A/D input. Now, on the A/D reference inputs, you need to keep Vrh less than or equal to Vdd. Likewise, you need to keep Vrl greater than or equal to ground. You should also keep Vrh and Vrl as close to their respective supplies as possible for the sake of A/D accuracy. Also, the spec that is referenced below about the Input Voltage being kept between - 0.3 to 7.0 volts, this is the maximums that you can put on the part without makeing it catch on fire or explode or something like that. The part is NOT guaranteed to work properly if you put 7.0 volts on an A/D input, it is only guaranteed to not be damaged. If the voltage on any pin exceeds Vdd by more than 0.3 volts, you will get significant current injection into the substrate and when that happens, all bets are off. You just don't know what will happen or exactly what threshold it will happen at. So, in actual operation, a package pin cannot go more than 0.3 volts above Vdd or below Vss. Regards, Charlie -----Original Message----- From: [mailto:] Sent: Monday, January 19, 2004 3:56 PM To: Subject: Re: [m68HC11] Analog to Digital Converter Inputs At 01:34 PM 19/01/04 -0500, you wrote: > >I don't see a maximum input voltage spec on the AD inputs?? The maximum >ratings lists "Input Voltage Vin 0.3 to +7.0" > The electrical model for the A/D converter shows a ~20V zener at the input. I thought it was higher than that but can't find the reference to it. Regards John Samperi ****************************************************** Ampertronics Pty. Ltd. 11 Brokenwood Place Baulkham Hills, NSW 2153 AUSTRALIA Tel. (02) 9674-6495 Fax (02) 9674-8745 Email: Website http://ampertronics.com.au * Electronic Design * Technical Services * Contract Assembly ****************************************************** |
Reply by ●January 20, 20042004-01-20
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-----Original Message----- From: Darrell N. [mailto:] Sent: Monday, January 19, 2004 6:52 PM To: Subject: Re: [m68HC11] Analog to Digital Converter Inputs Janet: > The AD reference voltage in this design can be varied from 0.4 V > to 4.0 V changing the sensitivity range. I don't believe the HC11 will work with this range. In the electrical spex, there is a <VR, which is minimum differential between VRH and VRL, and it is specified as 3V. It says performance is verified down to 2.5v differential, but accuracy is not guaranteed at this level. I agree this seems to be a problem according the spec, but I am not sure why accuracy is affected if ∆VR is reduced. Do you have any thoughts on this matter? > The AD input voltage can be as high as 11V. I don't think this is the case, either. For the converter to work, Vin must be less than VRH. In my experience, the chip will latch up if the A/D input is greater than VDD. It will destroy the input unless you have sufficient current limiting for the input (series resistor). I also believed that latch up can occur if the AD input is > than VRH. However, as noted by John Samperi, the AD input is protected by a 20V zener and the pink book (Sec 12.3) states that since “no P channel parasitics are directly connected to the AD input, latch up is not a problem”. However, I do not see an AD input spec relative to VRH and the pink book does not seem to address problems associated with driving an AD input > VRH??? > I don't see a maximum input voltage spec on the AD inputs?? The > maximum ratings lists "Input Voltage Vin 0.3 to +7.0" This is Absolute Maximum rating, ie the chip can be exposed to this voltage momentarily without damage. (Don't ask for a definition of "momentarily"). Continuous operation at this voltage will surely degrade the chip's performance permanently. > In my experience, I believe it is not advisable to overdrive the > analog to digital converter greater than VCC (in this case 5V) or > latch up can occur. Wise not to do so. Regards, Darrell Norquay Datalog Technology Inc. Calgary, Alberta, Canada Voice: (403) 243-2220 Fax: (403) 243-2872 Email: Web: www.datalog.ab.ca click here <http://rd.yahoo.com/SIGcbmg7em/M&7637.4116730.5333196.1261774/D=egroupweb/S06554205:HM/EXP74642737/A45637/R=0/*http:/www.netflix.com/Default?mqso`178397&partidA16730> <http://us.adserver.yahoo.com/l?M&7637.4116730.5333196.1261774/D=egroupmail/S=:HM/A45637/randc1768291 _____ > . |
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Reply by ●January 20, 20042004-01-20
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Janet: > I agree this seems to be a problem according the spec, but I am > not sure why accuracy is affected if ∆VR is reduced. Do you > have any thoughts on this matter? No. That would be a question for the boys at Motorola. I've often wanted to run VRH lower than 2.5V, let the list know if you get an answer to this. > I also believed that latch up can occur if the AD input is > than > VRH. However, as noted by John Samperi, the AD input is > protected by a 20V zener and the pink book (Sec 12.3) states that > since “no P channel parasitics are directly connected to the AD > input, latch up is not a problem”. However, I do not see an > AD input spec relative to VRH and the pink book does not seem to > address problems associated with driving an AD input > VRH??? Yes, it does say that, but later on it says that the current into an A/D pin should never get high enough to cause latchup. Go figure. Regards, Darrell Norquay Datalog Technology Inc. Calgary, Alberta, Canada Voice: (403) 243-2220 Fax: (403) 243-2872 Email: Web: www.datalog.ab.ca |
Reply by ●January 22, 20042004-01-22
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Your understanding is essentially correct. In my own designs, I take measures to prevent any ADC source signal from significantly exceeding Vdd (usually 5.0V on a HC11 design). The 'absolute maximum' specs might allow a AVref up to 7.0V, but I would not recommend AVref > 5.0V (or AVref > Vdd) myself. Also, to ensure best accuracy, mononticity, and differential linearity response, it is best to select a AVref that is the same voltage (approximately) as the device Vdd power supply. The wider the range between AVgnd and AVref, the more accurate your conversions will be, in general. If, as you say in your message, your signal source can go as high as 11V, you can use a simple resistor-divider to scale the level down to a 5.0V max level. Since the AD inputs of the HC11 are connected (when selected for conversion) to an internal capacitor of approx. 20pF, it is best to provide a low-impedance source to the device. A small part of the overall conversion time is allocated towards charging the sampling capacitor array, but a signal with too high of an impedance (>10K as I recall) will result in potentially inaccurate conversions, depending on the charge present (or not present) on the capacitor array from the previous conversion. The following circuit provides a fairly robust and error-safe signal for the HC11 (or any other uC that uses a switched-capacitor ADC input): . R1 Non-inverting D1 .Sig >---/\/\/---o follower (opamp) o--->|--- Vdd (+5) . | |\ | . o------/\/\/---o-------| |----/\/\/---o------------> To MCU ._|_ R2 |/ 470 | D2 .Gnd o---|<--- Vss (Gnd) Set R1 & R2 for the appropriate voltage division ratio. VOut = VIn * R2 / (R1 + R2) If VInV and desired VOut = 5V, suggest R1K and R2K. The op-amp follower (noninverting buffer) is suggested to ensure that a low-impedance source is provided to the microcontroller. The 470 ohm resistor and back-to-back diodes serve as a crude under/overvoltage clamp. This is not bulletproof since the diode drops will allow voltages 0.6V (approx) under/over Vss and Vdd to get through, but such overages should not damage the device as long as they are not prolonged. There are doubtless more sophisticated approaches that could be used to prevent under/overvoltages from reaching the MCU ADC input(s), but I find that this fairly simple arrangement serves for most applications. Since you mentioned that you were a EE, odds are you know more about such techniques than I do ;) The level of detail provided here is for the benefit of those who do not necessarily have a full EE background (which includes myself ;). --- In , "Janet Lefko" <jlefko@t...> wrote: > I am supporting a design that utilizes the AD converter. > > The AD reference voltage in this design can be varied from 0.4 V > to 4.0 V changing the sensitivity range. > > The AD input voltage can be as high as 11V. > > I don't see a maximum input voltage spec on the AD inputs?? > The maximum ratings lists "Input Voltage Vin 0.3 to +7.0" > > In my experience, I believe it is not advisable to overdrive the > analog to digital converter greater than VCC (in this case 5V) or > latch up can occur. > > Please advise. |
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Reply by ●January 22, 20042004-01-22
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--- In , "Mark Schultz" <n9xmj@y...> wrote: >............R1.......Non-inverting...........D1................. >..Sig >---/\/\/---o..follower.(opamp)....o--->|---.Vdd (+5)..... >..................|.......|\.............|...................... >...o------/\/\/---o-------|.|----/\/\/---o------------>.To.MCU.. >.._|_.......R2............|/......470....|...D2................. >..Gnd....................................o---|<---.Vss.(Gnd).... Ack! I don't know why the message system deems it necessary to corrupt my crude pictures. I've replaced spaces with periods above in the hope that it will come out formatted correctly. |
Reply by ●January 23, 20042004-01-23
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Thanks for your thorough explanation.
I am responsible for supporting and redesigning/updating the product (Pressure sensor data acquisition). I have decided to change the sensor op amps from LM324s driven with +/- 12V power to a dual supply +/- 5V op amp with rail to rail outputs. The LT1367, AD8032 are a few of the op amps I am considering. BTW, I got this job because of my prior experience with the HC11 although we will be upgrading to the HC12. I haven't considered another uP family, mainly because the HC12 is code compatible with the existing 12K HC11 code which I intend to modify where necessary, but not rewrite! I have a question about the VDD, VSS clamp diodes. I have used clamp diodes in the past but the pink book, Sec 12.3, states "External clamp diodes should be avoided, because of additional leakage currents, and this along with source resistance can degrade the signal". I still think clamp diodes could be used, if the source resistance is minimal ( the pink book gives some numbers and so does Mark) and I'm sure that with some research a low leakage diode could be selected. Janet Lefko Electrical Engineer Tekscan, Inc. 617 464-4500 x235 -----Original Message----- From: Mark Schultz [mailto:] Sent: Thursday, January 22, 2004 6:46 PM To: Subject: [m68HC11] Re: Analog to Digital Converter Inputs Your understanding is essentially correct. In my own designs, I take measures to prevent any ADC source signal from significantly exceeding Vdd (usually 5.0V on a HC11 design). The 'absolute maximum' specs might allow a AVref up to 7.0V, but I would not recommend AVref > 5.0V (or AVref > Vdd) myself. Also, to ensure best accuracy, mononticity, and differential linearity response, it is best to select a AVref that is the same voltage (approximately) as the device Vdd power supply. The wider the range between AVgnd and AVref, the more accurate your conversions will be, in general. If, as you say in your message, your signal source can go as high as 11V, you can use a simple resistor-divider to scale the level down to a 5.0V max level. Since the AD inputs of the HC11 are connected (when selected for conversion) to an internal capacitor of approx. 20pF, it is best to provide a low-impedance source to the device. A small part of the overall conversion time is allocated towards charging the sampling capacitor array, but a signal with too high of an impedance (>10K as I recall) will result in potentially inaccurate conversions, depending on the charge present (or not present) on the capacitor array from the previous conversion. The following circuit provides a fairly robust and error-safe signal for the HC11 (or any other uC that uses a switched-capacitor ADC input): . R1 Non-inverting D1 .Sig >---/\/\/---o follower (opamp) o--->|--- Vdd (+5) . | |\ | . o------/\/\/---o-------| |----/\/\/---o------------> To MCU ._|_ R2 |/ 470 | D2 .Gnd o---|<--- Vss (Gnd) Set R1 & R2 for the appropriate voltage division ratio. VOut = VIn * R2 / (R1 + R2) If VInV and desired VOut = 5V, suggest R1K and R2K. The op-amp follower (noninverting buffer) is suggested to ensure that a low-impedance source is provided to the microcontroller. The 470 ohm resistor and back-to-back diodes serve as a crude under/overvoltage clamp. This is not bulletproof since the diode drops will allow voltages 0.6V (approx) under/over Vss and Vdd to get through, but such overages should not damage the device as long as they are not prolonged. There are doubtless more sophisticated approaches that could be used to prevent under/overvoltages from reaching the MCU ADC input(s), but I find that this fairly simple arrangement serves for most applications. Since you mentioned that you were a EE, odds are you know more about such techniques than I do ;) The level of detail provided here is for the benefit of those who do not necessarily have a full EE background (which includes myself ;). --- In , "Janet Lefko" <jlefko@t...> wrote: > I am supporting a design that utilizes the AD converter. > > The AD reference voltage in this design can be varied from 0.4 V > to 4.0 V changing the sensitivity range. > > The AD input voltage can be as high as 11V. > > I don't see a maximum input voltage spec on the AD inputs?? > The maximum ratings lists "Input Voltage Vin 0.3 to +7.0" > > In my experience, I believe it is not advisable to overdrive the > analog to digital converter greater than VCC (in this case 5V) or > latch up can occur. > > Please advise. _____ > . |
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