People,
I'm reading DS of this device, and is not clear for me if the pins are
5V tolerant just in I/O functions, or if in second functions, like CAN
and UART this remains tolerants.
Thks,
leomecma
LPC2366 5V Tolerant pins
Started by ●September 21, 2007
Reply by ●September 21, 20072007-09-21
leomecma wrote:
>
> People,
> I'm reading DS of this device, and is not clear for me if the pins are
> 5V tolerant just in I/O functions, or if in second functions, like CAN
> and UART this remains tolerants.
>
You are confusing functional specs with electrical specs. Why would you
think that by changing the pin function that the electrical spec changes?
TomW
--
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net http://cyberiansoftware.com http://openzipit.org
"Windows? No thanks, I have work to do..."
----------------
>
> People,
> I'm reading DS of this device, and is not clear for me if the pins are
> 5V tolerant just in I/O functions, or if in second functions, like CAN
> and UART this remains tolerants.
>
You are confusing functional specs with electrical specs. Why would you
think that by changing the pin function that the electrical spec changes?
TomW
--
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net http://cyberiansoftware.com http://openzipit.org
"Windows? No thanks, I have work to do..."
----------------
Reply by ●September 21, 20072007-09-21
If you intend to use ADC converter, and apply more then 3 volts in it's pin
you will have wrong results.
if you have 5 volts at ADC1, and try to read ADC2 eventhough the voltage is right you will have wrong result.
Edriano Carlos de Arao
STP Tecnologia ind.e com. Ltda
Al Juari, 447 - Centro Empresarial Tamborbr /> Barueri, SP
Cep 06460-090
Fone +55 11 41952396
----- Original Message -----
From: leomecma
To: l...
Sent: Friday, September 21, 2007 12:03 PM
Subject: [lpc2000] LPC2366 5V Tolerant pins
People,
I'm reading DS of this device, and is not clear for me if the pins are
5V tolerant just in I/O functions, or if in second functions, like CAN
and UART this remains tolerants.
Thks,
leomecma
if you have 5 volts at ADC1, and try to read ADC2 eventhough the voltage is right you will have wrong result.
Edriano Carlos de Arao
STP Tecnologia ind.e com. Ltda
Al Juari, 447 - Centro Empresarial Tamborbr /> Barueri, SP
Cep 06460-090
Fone +55 11 41952396
----- Original Message -----
From: leomecma
To: l...
Sent: Friday, September 21, 2007 12:03 PM
Subject: [lpc2000] LPC2366 5V Tolerant pins
People,
I'm reading DS of this device, and is not clear for me if the pins are
5V tolerant just in I/O functions, or if in second functions, like CAN
and UART this remains tolerants.
Thks,
leomecma
Reply by ●September 21, 20072007-09-21
Because, when I change internal functions I can have a internal MUX that put pin
in another
circuit, that can be not 5V tolerant.
My questions is: all pins except these are A/D, accept 5V?
leomecma wrote:
>
> People,
> I'm reading DS of this device, and is not clear for me if the pins are
> 5V tolerant just in I/O functions, or if in second functions, like CAN
> and UART this remains tolerants.
>
You are confusing functional specs with electrical specs. Why would you
think that by changing the pin function that the electrical spec changes?
TomW
--
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net http://cyberiansoftware.com http://openzipit.org
"Windows? No thanks, I have work to do..."
----------------
circuit, that can be not 5V tolerant.
My questions is: all pins except these are A/D, accept 5V?
leomecma wrote:
>
> People,
> I'm reading DS of this device, and is not clear for me if the pins are
> 5V tolerant just in I/O functions, or if in second functions, like CAN
> and UART this remains tolerants.
>
You are confusing functional specs with electrical specs. Why would you
think that by changing the pin function that the electrical spec changes?
TomW
--
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net http://cyberiansoftware.com http://openzipit.org
"Windows? No thanks, I have work to do..."
----------------
Reply by ●September 21, 20072007-09-21
Leo wrote:
>
> Because, when I change internal functions I can have a internal MUX
> that put pin in another
> circuit, that can be not 5V tolerant.
>
The electrical spec is referring to what you call the MUX. As the
other poster pointed out that just because a pin is 5 volt tolerant
would not allow the ADC to function correctly at that voltage.
You ask a general question, you get a general answer.
Regards,
TomW
--
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net http://cyberiansoftware.com http://openzipit.org
"Windows? No thanks, I have work to do..."
----------------
>
> Because, when I change internal functions I can have a internal MUX
> that put pin in another
> circuit, that can be not 5V tolerant.
>
The electrical spec is referring to what you call the MUX. As the
other poster pointed out that just because a pin is 5 volt tolerant
would not allow the ADC to function correctly at that voltage.
You ask a general question, you get a general answer.
Regards,
TomW
--
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net http://cyberiansoftware.com http://openzipit.org
"Windows? No thanks, I have work to do..."
----------------
Reply by ●September 22, 20072007-09-22
--- In l..., Tom Walsh wrote:
>
> Leo wrote:
> >
> > Because, when I change internal functions I can have a internal MUX
> > that put pin in another
> > circuit, that can be not 5V tolerant.
> > The electrical spec is referring to what you call the MUX. As the
> other poster pointed out that just because a pin is 5 volt tolerant
> would not allow the ADC to function correctly at that voltage.
>
> You ask a general question, you get a general answer.
>
> Regards,
>
> TomW
Then too, you have to read the fine print. You can not put a 5V
signal on a pin if Vdd is not present. If you did, the body diodes
won't have a place to dump the excess voltage (the power supply) and
will instead power up the core at 5V. My guess is that the magic
smoke will leak out.
I would avoid 5V tolerance in the same way I would avoid IAP. These
are marketing ideas that don't look as clever when viewed as a system
designer.
Richard
>
> Leo wrote:
> >
> > Because, when I change internal functions I can have a internal MUX
> > that put pin in another
> > circuit, that can be not 5V tolerant.
> > The electrical spec is referring to what you call the MUX. As the
> other poster pointed out that just because a pin is 5 volt tolerant
> would not allow the ADC to function correctly at that voltage.
>
> You ask a general question, you get a general answer.
>
> Regards,
>
> TomW
Then too, you have to read the fine print. You can not put a 5V
signal on a pin if Vdd is not present. If you did, the body diodes
won't have a place to dump the excess voltage (the power supply) and
will instead power up the core at 5V. My guess is that the magic
smoke will leak out.
I would avoid 5V tolerance in the same way I would avoid IAP. These
are marketing ideas that don't look as clever when viewed as a system
designer.
Richard
Reply by ●September 24, 20072007-09-24
I was interested in the 5V tolerant phrase for pins.
It's in the 2119/2129 documentation as global/summary statement.
But I couldn't see any specification, clarification, qualification for it.
Can anyone give a reference on this (authorative not speculative).
My purpose would be for interfacing to 5V ICs.
David Jones
Software Developer (Embedded Systems)
Victorian Partnership for Advanced Computing (VPAC)
Microsoft Partner # 2092327
d...@vpac.org
+61 3 99258340
+61 3 99254647
Blog: http://ce-aus.spaces.live.com/
Skype: David.Aus.Jones
Windows CE and XP Embedded Trainer/Consultant
Compact Framework
Embedded Systems (Micros)
System Integration
It's in the 2119/2129 documentation as global/summary statement.
But I couldn't see any specification, clarification, qualification for it.
Can anyone give a reference on this (authorative not speculative).
My purpose would be for interfacing to 5V ICs.
David Jones
Software Developer (Embedded Systems)
Victorian Partnership for Advanced Computing (VPAC)
Microsoft Partner # 2092327
d...@vpac.org
+61 3 99258340
+61 3 99254647
Blog: http://ce-aus.spaces.live.com/
Skype: David.Aus.Jones
Windows CE and XP Embedded Trainer/Consultant
Compact Framework
Embedded Systems (Micros)
System Integration
Reply by ●September 24, 20072007-09-24
David Jones wrote:
>
> I was interested in the 5V tolerant phrase for pins.
>
> It's in the 2119/2129 documentation as global/summary statement.
>
> But I couldn't see any specification, clarification, qualification for it.
>
> Can anyone give a reference on this (authorative not speculative) .
>
> My purpose would be for interfacing to 5V ICs.
>
Ok, lets understand what happens with "5V Tolerant Pins" when connecting
such pins to a processor that uses a lower I/O supply (e.g. 3.3volts).
The extra voltage has to go somewhere. At worst case, you have
1.2volts, at so many milli / micro amperes of current that has to go
someplace. Where does it go?
The excess power (watts) gets dumped into the 3.3volt supply via
clamping diodes placed at the processor pin and are connected to the I/O
supply rail. While the power is low (watts) and the 3.3volt supply can
handle dissipating the excess power, a problem may occur at the
processor pin area of the silicon. The wattage being dumped across the
clamping diode shows up as heat. Too much heat will degrade the
lifetime of the silicon faster than the silicon would normally age.
The amount of heat generated depends on the source resistance of the
5volt gate / device / whatever that is connected to that processor pin.
Too low a source resistance and POOF(!), you let out the magic-smoke.
However, if the source resistance is not too low, you will only heat up
the junction and abuse the silicon over time.
While "5v Tolerant Pins" can be an asset in a carefully designed system,
many times they can dramatically shorten a products' lifetime. What you
really should be looking at first is a Level Shifter type of IC to stand
between the processor pin and the 5volt device. A level shifter is
designed specifically to avoid some of the heating / source resistance
problems I mentioned.
If you are not sure, consult your resident EE for an further explanation
/ solution.
Regards,
TomW
--
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net http://cyberiansoftware.com http://openzipit.org
"Windows? No thanks, I have work to do..."
----------------
>
> I was interested in the 5V tolerant phrase for pins.
>
> It's in the 2119/2129 documentation as global/summary statement.
>
> But I couldn't see any specification, clarification, qualification for it.
>
> Can anyone give a reference on this (authorative not speculative) .
>
> My purpose would be for interfacing to 5V ICs.
>
Ok, lets understand what happens with "5V Tolerant Pins" when connecting
such pins to a processor that uses a lower I/O supply (e.g. 3.3volts).
The extra voltage has to go somewhere. At worst case, you have
1.2volts, at so many milli / micro amperes of current that has to go
someplace. Where does it go?
The excess power (watts) gets dumped into the 3.3volt supply via
clamping diodes placed at the processor pin and are connected to the I/O
supply rail. While the power is low (watts) and the 3.3volt supply can
handle dissipating the excess power, a problem may occur at the
processor pin area of the silicon. The wattage being dumped across the
clamping diode shows up as heat. Too much heat will degrade the
lifetime of the silicon faster than the silicon would normally age.
The amount of heat generated depends on the source resistance of the
5volt gate / device / whatever that is connected to that processor pin.
Too low a source resistance and POOF(!), you let out the magic-smoke.
However, if the source resistance is not too low, you will only heat up
the junction and abuse the silicon over time.
While "5v Tolerant Pins" can be an asset in a carefully designed system,
many times they can dramatically shorten a products' lifetime. What you
really should be looking at first is a Level Shifter type of IC to stand
between the processor pin and the 5volt device. A level shifter is
designed specifically to avoid some of the heating / source resistance
problems I mentioned.
If you are not sure, consult your resident EE for an further explanation
/ solution.
Regards,
TomW
--
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net http://cyberiansoftware.com http://openzipit.org
"Windows? No thanks, I have work to do..."
----------------
Reply by ●September 24, 20072007-09-24
--- In l..., Tom Walsh wrote:
> Ok, lets understand what happens with "5V Tolerant Pins" when
connecting
> such pins to a processor that uses a lower I/O supply (e.g. 3.3volts).
> The extra voltage has to go somewhere. At worst case, you have
> 1.2volts, at so many milli / micro amperes of current that has to go
> someplace. Where does it go?
>
> The excess power (watts) gets dumped into the 3.3volt supply via
> clamping diodes placed at the processor pin and are connected to the
I/O
> supply rail. While the power is low (watts) and the 3.3volt supply can
> handle dissipating the excess power, a problem may occur at the
> processor pin area of the silicon. The wattage being dumped across the
> clamping diode shows up as heat. Too much heat will degrade the
> lifetime of the silicon faster than the silicon would normally age.
>
> The amount of heat generated depends on the source resistance of the
> 5volt gate / device / whatever that is connected to that processor
pin.
> Too low a source resistance and POOF(!), you let out the magic-smoke.
Hi Tom,
I believe that you are assuming that there is a single clamping diode
from GPIO pin to the 3.3V rail and that the current must be limited by
the external impedance. I have not found any documentation that would
confirm that to be the case.
In fact, since they do not specify a maximum input current for the
GPIO pins, I strongly suspect that this is not the case. In other
words, I believe that you could tie a GPIO pin directly to a 5V rail
and not experience any heat/damage.
My guess is that they have a "string" of diodes (at Vf ~0.5V each)
that can drop 5 volts to 3.3 volts before clamping (and this would
explain the requirement that 3.3 volts be present to allow 5V tolerance).
There are lots of logic families (e.g. 74LVC) that can be used for
level translation without the need for a 5V supply rail. I see no
reason that the LPC family could not include the same type of circuitry.
Best regards, Scott.
> Ok, lets understand what happens with "5V Tolerant Pins" when
connecting
> such pins to a processor that uses a lower I/O supply (e.g. 3.3volts).
> The extra voltage has to go somewhere. At worst case, you have
> 1.2volts, at so many milli / micro amperes of current that has to go
> someplace. Where does it go?
>
> The excess power (watts) gets dumped into the 3.3volt supply via
> clamping diodes placed at the processor pin and are connected to the
I/O
> supply rail. While the power is low (watts) and the 3.3volt supply can
> handle dissipating the excess power, a problem may occur at the
> processor pin area of the silicon. The wattage being dumped across the
> clamping diode shows up as heat. Too much heat will degrade the
> lifetime of the silicon faster than the silicon would normally age.
>
> The amount of heat generated depends on the source resistance of the
> 5volt gate / device / whatever that is connected to that processor
pin.
> Too low a source resistance and POOF(!), you let out the magic-smoke.
Hi Tom,
I believe that you are assuming that there is a single clamping diode
from GPIO pin to the 3.3V rail and that the current must be limited by
the external impedance. I have not found any documentation that would
confirm that to be the case.
In fact, since they do not specify a maximum input current for the
GPIO pins, I strongly suspect that this is not the case. In other
words, I believe that you could tie a GPIO pin directly to a 5V rail
and not experience any heat/damage.
My guess is that they have a "string" of diodes (at Vf ~0.5V each)
that can drop 5 volts to 3.3 volts before clamping (and this would
explain the requirement that 3.3 volts be present to allow 5V tolerance).
There are lots of logic families (e.g. 74LVC) that can be used for
level translation without the need for a 5V supply rail. I see no
reason that the LPC family could not include the same type of circuitry.
Best regards, Scott.
Reply by ●September 24, 20072007-09-24
--- In l..., "jsm09a"
wrote:
>
> --- In l..., Tom Walsh wrote:
>
> > Ok, lets understand what happens with "5V Tolerant Pins" when
> connecting
> > such pins to a processor that uses a lower I/O supply (e.g.
3.3volts).
> > The extra voltage has to go somewhere. At worst case, you have
> > 1.2volts, at so many milli / micro amperes of current that has to go
> > someplace. Where does it go?
> >
> > The excess power (watts) gets dumped into the 3.3volt supply via
> > clamping diodes placed at the processor pin and are connected to the
> I/O
> > supply rail. While the power is low (watts) and the 3.3volt
supply can
> > handle dissipating the excess power, a problem may occur at the
> > processor pin area of the silicon. The wattage being dumped
across the
> > clamping diode shows up as heat. Too much heat will degrade the
> > lifetime of the silicon faster than the silicon would normally age.
> >
> > The amount of heat generated depends on the source resistance of the
> > 5volt gate / device / whatever that is connected to that processor
> pin.
> > Too low a source resistance and POOF(!), you let out the
magic-smoke.
>
> Hi Tom,
>
> I believe that you are assuming that there is a single clamping diode
> from GPIO pin to the 3.3V rail and that the current must be limited by
> the external impedance. I have not found any documentation that would
> confirm that to be the case.
>
> In fact, since they do not specify a maximum input current for the
> GPIO pins, I strongly suspect that this is not the case. In other
> words, I believe that you could tie a GPIO pin directly to a 5V rail
> and not experience any heat/damage.
But the point is, they don't specify it. There doesn't appear to be a
document describing, in detail, just what 5V tolerance means. There
is a document for the LPC900 family:
http://www.nxp.com/acrobat_download/applicationnotes/AN10220_1.pdf
>
> My guess is that they have a "string" of diodes (at Vf ~0.5V each)
> that can drop 5 volts to 3.3 volts before clamping (and this would
> explain the requirement that 3.3 volts be present to allow 5V
tolerance).
I think it might be a little more complicated than that. Using this
idea, they could string a lot more diodes and be 10V CMOS tolerant.
Regardless of how they clamp, the voltage continues into the core at a
high level. The more series diodes, the higher that voltage can get.
Many chips (I am thinking about Xilinx Spartan IIE and Spartan 3
FPGAs) have 5V tolerance when used with external current limiting
resistors. It is a given that the body diode will clamp to Vdd + Vf
(which might be 0.2V for a Schottky diode) so the resistor is
calculated to limit heating.
Given that CMOS inputs have no appreciable input current, it would be
easy enough to build the current limiting resistor inside the chip
between the pin and the body diode.
Richard
wrote:
>
> --- In l..., Tom Walsh wrote:
>
> > Ok, lets understand what happens with "5V Tolerant Pins" when
> connecting
> > such pins to a processor that uses a lower I/O supply (e.g.
3.3volts).
> > The extra voltage has to go somewhere. At worst case, you have
> > 1.2volts, at so many milli / micro amperes of current that has to go
> > someplace. Where does it go?
> >
> > The excess power (watts) gets dumped into the 3.3volt supply via
> > clamping diodes placed at the processor pin and are connected to the
> I/O
> > supply rail. While the power is low (watts) and the 3.3volt
supply can
> > handle dissipating the excess power, a problem may occur at the
> > processor pin area of the silicon. The wattage being dumped
across the
> > clamping diode shows up as heat. Too much heat will degrade the
> > lifetime of the silicon faster than the silicon would normally age.
> >
> > The amount of heat generated depends on the source resistance of the
> > 5volt gate / device / whatever that is connected to that processor
> pin.
> > Too low a source resistance and POOF(!), you let out the
magic-smoke.
>
> Hi Tom,
>
> I believe that you are assuming that there is a single clamping diode
> from GPIO pin to the 3.3V rail and that the current must be limited by
> the external impedance. I have not found any documentation that would
> confirm that to be the case.
>
> In fact, since they do not specify a maximum input current for the
> GPIO pins, I strongly suspect that this is not the case. In other
> words, I believe that you could tie a GPIO pin directly to a 5V rail
> and not experience any heat/damage.
But the point is, they don't specify it. There doesn't appear to be a
document describing, in detail, just what 5V tolerance means. There
is a document for the LPC900 family:
http://www.nxp.com/acrobat_download/applicationnotes/AN10220_1.pdf
>
> My guess is that they have a "string" of diodes (at Vf ~0.5V each)
> that can drop 5 volts to 3.3 volts before clamping (and this would
> explain the requirement that 3.3 volts be present to allow 5V
tolerance).
I think it might be a little more complicated than that. Using this
idea, they could string a lot more diodes and be 10V CMOS tolerant.
Regardless of how they clamp, the voltage continues into the core at a
high level. The more series diodes, the higher that voltage can get.
Many chips (I am thinking about Xilinx Spartan IIE and Spartan 3
FPGAs) have 5V tolerance when used with external current limiting
resistors. It is a given that the body diode will clamp to Vdd + Vf
(which might be 0.2V for a Schottky diode) so the resistor is
calculated to limit heating.
Given that CMOS inputs have no appreciable input current, it would be
easy enough to build the current limiting resistor inside the chip
between the pin and the body diode.
Richard
