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LPC2148, PLL0CFG register

Started by richdinoso October 30, 2008
When I enter main, bits 4:0 of PLL0CFG = 4 (those are the MSEL bits).
I was curious why this is the case, because page 30 of the user manual
says the reset value for the MSEL bits = 0.

Is MSEL being changed before main? I'm using the Crossworks compiler.

--- Rich

An Engineer's Guide to the LPC2100 Series

If you used the default startup file that Crossworks uses, then it set
up the PLL.

Jeff

--- In l..., "richdinoso" wrote:
>
> When I enter main, bits 4:0 of PLL0CFG = 4 (those are the MSEL bits).
> I was curious why this is the case, because page 30 of the user
manual
> says the reset value for the MSEL bits = 0.
>
> Is MSEL being changed before main? I'm using the Crossworks compiler.
>
> --- Rich
>

Thanks Jeff. Is that the crt0.s file?

--- In l..., "ksdoubleshooter" wrote:
>
> If you used the default startup file that Crossworks uses, then it set
> up the PLL.
>
> Jeff
>
> --- In l..., "richdinoso" wrote:
> >
> > When I enter main, bits 4:0 of PLL0CFG = 4 (those are the MSEL bits).
> > I was curious why this is the case, because page 30 of the user
> manual
> > says the reset value for the MSEL bits = 0.
> >
> > Is MSEL being changed before main? I'm using the Crossworks compiler.
> >
> > --- Rich
>
--- In l..., "richdinoso" wrote:
>
> Is that the crt0.s file?
>

The Crossworks crt0.s file is described here:

http://www.rowley.co.uk/documentation/arm_1_7/arm_crt0.htm

... and the general startup process here:

http://www.rowley.co.uk/documentation/arm_1_7/arm_target_support.htm

Chris Burrows
Armaide: Oberon-07 ARM Development System for Windows
http://www.armaide.com