> With many FPGAs having some kind of dual-port BlockRAM, it is quite
> easy to have FIFOs to smooth out the processing. Still, trying to
> clock data into BlockRAM at 20 MHz takes a pretty fast FPGA.

The low-end Altera Cyclone series of devices, and Xilinx Spartan
devices all work fine at 100MHz or more. You just have to use the
RAM in synchronous (pipelined) mode (which is pretty much all
the newer devices support anyway).

Cheers,
Dave

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