Hi,
Since some of Philips's people seem to be reading this group. How many
people
think they should change the crappy PC compatible UARTs to something else ?
UARTS that can generate interrupt when the last bit has been transmitted to
make it easier to switch a RS-485 buffer for example. A proper 9 bit mode.
The possibility to read how many characters are in the Rx or Tx FIFO ? etc.
Regards
Anton Erasmus
--
A J Erasmus
Who thinks the PC Compatible UARTs on the LPC are nice ?
Started by ●April 12, 2005
Reply by ●April 12, 20052005-04-12
I would've preferred the 28LC92 UART instead. In fact, this part is an
original Philips architecture, based on the very fine SCC2692 I
believe!
Ken Wada
--- In lpc2000@lpc2..., "Anton Erasmus" <antone@s...> wrote:
> Hi,
>
> Since some of Philips's people seem to be reading this group. How
many people
> think they should change the crappy PC compatible UARTs to something
else ?
> UARTS that can generate interrupt when the last bit has been
transmitted to
> make it easier to switch a RS-485 buffer for example. A proper 9 bit
mode.
> The possibility to read how many characters are in the Rx or Tx FIFO
? etc.
>
>
> Regards
> Anton Erasmus > --
> A J Erasmus
Reply by ●April 13, 20052005-04-13
At 07:31 PM 4/12/05 +0200, Anton Erasmus wrote:
>Since some of Philips's people seem to be reading this group. How many people
>think they should change the crappy PC compatible UARTs to something else ?
>UARTS that can generate interrupt when the last bit has been transmitted to
>make it easier to switch a RS-485 buffer for example. A proper 9 bit mode.
>The possibility to read how many characters are in the Rx or Tx FIFO ? etc.
I can see the utility of a proper 9 bit mode with an interrupt after last
transmitted bit available. On the FIFO side though the addition of a flag
to indicate that the transmit FIFO was full along with an interrupt to
indicate when it was say 1/2 full would be enough to keep the transmit
buffer full under just about all conditions. The receive side seems quite
sufficient to me.
Another item that might be useful would be some LIN specific support,
mostly more break detection support.
Robert " 'Freedom' has no meaning of itself. There are always restrictions, be
they legal, genetic, or physical. If you don't believe me, try to chew a
radio signal. " -- Kelvin Throop, III
http://www.aeolusdevelopment.com/
>Since some of Philips's people seem to be reading this group. How many people
>think they should change the crappy PC compatible UARTs to something else ?
>UARTS that can generate interrupt when the last bit has been transmitted to
>make it easier to switch a RS-485 buffer for example. A proper 9 bit mode.
>The possibility to read how many characters are in the Rx or Tx FIFO ? etc.
I can see the utility of a proper 9 bit mode with an interrupt after last
transmitted bit available. On the FIFO side though the addition of a flag
to indicate that the transmit FIFO was full along with an interrupt to
indicate when it was say 1/2 full would be enough to keep the transmit
buffer full under just about all conditions. The receive side seems quite
sufficient to me.
Another item that might be useful would be some LIN specific support,
mostly more break detection support.
Robert " 'Freedom' has no meaning of itself. There are always restrictions, be
they legal, genetic, or physical. If you don't believe me, try to chew a
radio signal. " -- Kelvin Throop, III
http://www.aeolusdevelopment.com/
Reply by ●April 13, 20052005-04-13
> I can see the utility of a proper 9 bit mode with an interrupt
after
last
> transmitted bit available.
Some of Exar's latest UART's are quite nice and feature options such
as 9 bit protocol, automatic RS485 direction switching, etc. Face it,
the 16c550 format is a relic, I would gladly swap these for 9 bit
UART's, even if unbuffered. For now I'm happily using Freescale
MC9S12E's in communications applications, it has three nice 9 bit
UART's.
Of course you can force 9 bit protocol on a 16c55x by reprogramming
the parity bit for each character, but it's a lot of work and you
can't use the buffer.
Here's the Exar UART matrix...
http://www.exar.com/search_uart.php
Bill T.
http://www.kupercontrols.com
Reply by ●April 14, 20052005-04-14
--- In lpc2000@lpc2..., "Anton Erasmus" <antone@s...> wrote:
> Hi,
>
> Since some of Philips's people seem to be reading this group. How
many people
> think they should change the crappy PC compatible UARTs to
something else ?
> UARTS that can generate interrupt when the last bit has been
transmitted to
> make it easier to switch a RS-485 buffer for example. A proper 9
bit mode.
> The possibility to read how many characters are in the Rx or Tx
FIFO ? etc.
>
>
> Regards
> Anton Erasmus > --
> A J Erasmus
YES! YES! YES!
The most annoying thing is that the time when THRE interrupt occurs
is dependent on "initialization conditions."
Second is that there is no way to tell if the transmit FIFO is full.
Reply by ●April 14, 20052005-04-14
Am I missing something here guys (and gals)? When the FIFO is
enabled the THRE bit in the Line Status Register is set whenever
the FIFO can accept additional characters. So if it were clear,
isn't that an indication the FIFO is full?
As for RS-485 transceiver turn-around; the TEMT bit also in the
Line Status Register, can be used to determine when the stop bit
of the last character has been transmitted. Can't that be used
to control the RS-485 interface?
Regards
-Bill Knight
R O SoftWare &
http://www.theARMPatch.com
enabled the THRE bit in the Line Status Register is set whenever
the FIFO can accept additional characters. So if it were clear,
isn't that an indication the FIFO is full?
As for RS-485 transceiver turn-around; the TEMT bit also in the
Line Status Register, can be used to determine when the stop bit
of the last character has been transmitted. Can't that be used
to control the RS-485 interface?
Regards
-Bill Knight
R O SoftWare &
http://www.theARMPatch.com
Reply by ●April 14, 20052005-04-14
--- In lpc2000@lpc2..., "Bill Knight" <BillK@t...> wrote:
> Am I missing something here guys (and gals)? When the FIFO is
> enabled the THRE bit in the Line Status Register is set whenever
> the FIFO can accept additional characters. So if it were clear,
> isn't that an indication the FIFO is full?
> As for RS-485 transceiver turn-around; the TEMT bit also in the
> Line Status Register, can be used to determine when the stop bit
> of the last character has been transmitted. Can't that be used
> to control the RS-485 interface?
>
> Regards
> -Bill Knight
> R O SoftWare &
> http://www.theARMPatch.com
I second that motion. I am using the THRE bit in the LSR to
determine
whether the transmit FIFO is full and it works fine.
JT
Reply by ●April 14, 20052005-04-14
The THRE is set when the FIFO is empty. There may still be a BYTE in the
transmit
shift register, but to keep the flow going you have to respond in less
than 1 byte transmit
time to the THRE interrupt. If you don't there is nothing lost, the
transmission just takes
a bit longer.
Regards,
Richard. Bill Knight wrote:
> Am I missing something here guys (and gals)? When the FIFO is
> enabled the THRE bit in the Line Status Register is set whenever
> the FIFO can accept additional characters. So if it were clear,
> isn't that an indication the FIFO is full?
> As for RS-485 transceiver turn-around; the TEMT bit also in the
> Line Status Register, can be used to determine when the stop bit
> of the last character has been transmitted. Can't that be used
> to control the RS-485 interface?
>
> Regards
> -Bill Knight
> R O SoftWare &
> http://www.theARMPatch.com > *>.
transmit
shift register, but to keep the flow going you have to respond in less
than 1 byte transmit
time to the THRE interrupt. If you don't there is nothing lost, the
transmission just takes
a bit longer.
Regards,
Richard. Bill Knight wrote:
> Am I missing something here guys (and gals)? When the FIFO is
> enabled the THRE bit in the Line Status Register is set whenever
> the FIFO can accept additional characters. So if it were clear,
> isn't that an indication the FIFO is full?
> As for RS-485 transceiver turn-around; the TEMT bit also in the
> Line Status Register, can be used to determine when the stop bit
> of the last character has been transmitted. Can't that be used
> to control the RS-485 interface?
>
> Regards
> -Bill Knight
> R O SoftWare &
> http://www.theARMPatch.com > *>.
Reply by ●April 14, 20052005-04-14
Indeed!
You need...actually it is a very good idea to use the TEMT bit to
toggle the transmit enable bit on your RS-485 interface.
For me, it would have been nice to have the TEMT bit generate an
interrupt. My code would have been a little bit more efficient in this
way.
As it stands, I now look for a signal that the interrupt service
routine has processed the last byte out, (THRE interrupt, and no more
bytes in tx queue). After this, I poll the TEMT bit. This lets me know
that I will not 'clobber' that last byte out before disabling the
transmitter on my RS-485 transceiver.
Ken Wada
--- In lpc2000@lpc2..., "Bill Knight" <BillK@t...> wrote:
> Am I missing something here guys (and gals)? When the FIFO is
> enabled the THRE bit in the Line Status Register is set whenever
> the FIFO can accept additional characters. So if it were clear,
> isn't that an indication the FIFO is full?
> As for RS-485 transceiver turn-around; the TEMT bit also in the
> Line Status Register, can be used to determine when the stop bit
> of the last character has been transmitted. Can't that be used
> to control the RS-485 interface?
>
> Regards
> -Bill Knight
> R O SoftWare &
> http://www.theARMPatch.com
Reply by ●April 14, 20052005-04-14
> Second is that there is no way to tell if the transmit FIFO is full.
Heh...
you need to ASSUME, that when THRE gets generated, that you can stuff
up to 16-bytes into that FIFO.
Actually, my experience has shown that this is a pretty good
assumption.
Unfortunately, if you work under non-interrupt mode, this means you
need to wait for the queue to completely drain before you can feel
'safe' in stuffing more bytes into the queue....
not the most efficient means to go in non-interrupt mode.
Ken Wada
