Hi All

I am perusing the '449 manual (SLAU056C) and in the digital IO 
section it says

'An external interrupt event should be at least 1.5 times MCLK or 
longer, to ensure it is accepted...'

Does this mean that the external interrupt can not be used to exit 
low power mode, since MCLK is turned off in all low power modes?

Regards
David Bagnara

You can wake from all except LPM4 via the port ints.  I interpreted that
confusing statement to mean that there is indeed some minimum trigger width,
and I assumed the then-active clock source determined it, so I applied the
1.5x rule to ACLK.  But I'd like to hear from some experts on it...

--Bruce



> 'An external interrupt event should be at
least 1.5 times MCLK or
> longer, to ensure it is accepted...'
>
> Does this mean that the external interrupt can not be used to exit
> low power mode, since MCLK is turned off in all low power modes?
>
> Regards
> David Bagnara

----- Original Message -----
From: "Bruce Cannon" <bc@bc@....>
To: <msp430@msp4...>
Sent: Thursday, May 27, 2004 2:11 AM
Subject: RE: [msp430] external interrupt in low power mode


> You can wake from all except LPM4 via the port
ints.  I interpreted that
> confusing statement to mean that there is indeed some minimum trigger
width,
> and I assumed the then-active clock source
determined it, so I applied the
> 1.5x rule to ACLK.  But I'd like to hear from some experts on it...

Why except LPM4?

See eg. http://focus.ti.com/lit/an/slaa139/slaa139.pdf

Albert

> > You can wake from all except LPM4 via the port ints.  I
interpreted that
> > confusing statement to mean that there is
indeed some minimum trigger
> width,
> > and I assumed the then-active clock source determined it, so I applied
the
> > 1.5x rule to ACLK.  But I'd like to hear from some experts on
it...

It depends on the kind of interrupt "filtering".
In this case there is none since you can wake up from LPM4.
The min. pulse width will only be determined by the min. time needed to
trigger the flip-flop.

In contrast, filtering on pins is typically implemented with a clocked setup,
thus you would need *some* kind of clock, hence Bruce's query on LPM4.

This can be applied on general logic as well.
Typically you use a series of D FlipFlops clocked sync as a shiftregister,
# of FFs is equal to how many clocks the input needs to be valid.
All outputs of D FFs are ANDed together onto J input of JK flipflop, and
all NOT outputs ANDed together onto K input of JK FF, with same clock.
The JK FF asserts Q when a valid signal is detected for # of DFF clocks
(ie. filtered H/L).

Clearly the MSP430 does not use this sort of setup, since it can wake up
from LPM4 on P1/P2 INTs, which is common, but it does not protect against
short glitches in lieu of absence of clock.

-- Kris

On Thu, May 27, 2004 at 05:44:48PM +1000, microbit wrote:

> In contrast, filtering on pins is typically
implemented with a clocked setup,
> thus you would need *some* kind of clock, hence Bruce's query on LPM4.
> 
> This can be applied on general logic as well.
> Typically you use a series of D FlipFlops clocked sync as a shiftregister,
> # of FFs is equal to how many clocks the input needs to be valid.
> All outputs of D FFs are ANDed together onto J input of JK flipflop, and
> all NOT outputs ANDed together onto K input of JK FF, with same clock.
> The JK FF asserts Q when a valid signal is detected for # of DFF clocks
> (ie. filtered H/L).
> 
> Clearly the MSP430 does not use this sort of setup, since it can wake up
> from LPM4 on P1/P2 INTs, which is common, but it does not protect against
> short glitches in lieu of absence of clock.

It does:
"Any external interrupt event should be at least 1.5 times MCLK or longer,
to
ensure that it is accepted and the corresponding interrupt flag is set."

I guess they use a separate logic from all inputs to the DCO, 
the DCO starts (6us) and then the external interrupt pins are sensed in the 
next MCLK cycle. 
So I think my simple RC-watchdog at one onterrupt pin should work (detecting
faulty 32kHz clock, see other thread).

        Matthias

Matthias Weingart wrote:
> On Thu, May 27, 2004 at 05:44:48PM +1000,
microbit wrote:
> 
> 
>>In contrast, filtering on pins is typically implemented with a clocked
setup,
>>thus you would need *some* kind of clock, hence Bruce's query on
LPM4.
>>
>>This can be applied on general logic as well.
>>Typically you use a series of D FlipFlops clocked sync as a
shiftregister,
>># of FFs is equal to how many clocks the input needs to be valid.
>>All outputs of D FFs are ANDed together onto J input of JK flipflop, and
>>all NOT outputs ANDed together onto K input of JK FF, with same clock.
>>The JK FF asserts Q when a valid signal is detected for # of DFF clocks
>>(ie. filtered H/L).
>>
>>Clearly the MSP430 does not use this sort of setup, since it can wake up
>>from LPM4 on P1/P2 INTs, which is common, but it does not protect
against
>>short glitches in lieu of absence of clock.
> 
> 
> It does:
> "Any external interrupt event should be at least 1.5 times MCLK or
longer, to
> ensure that it is accepted and the corresponding interrupt flag is
set."
> 
> I guess they use a separate logic from all inputs to the DCO, 
> the DCO starts (6us) and then the external interrupt pins are sensed in the

> next MCLK cycle. 
> So I think my simple RC-watchdog at one onterrupt pin should work
(detecting
> faulty 32kHz clock, see other thread).
> 
>         Matthias

The User Guide and individual data sheets are extremely slack in this 
area. They display the port pin logic, where it can be clearly seen that 
the generation of the P1IRQx signal to the interrupt logic is a logic 
function requiring no clokc, in fact it probably acts as a clock signal 
itself (being denoted as edge sensitive only, not level sensitive). 
Unfortunately I have not been able to find a hardware representation of 
the maskable interrupt logic to establish the exact function beyond this 
point. Suffice to say that pin interrupts will wake the processor from 
LPM4 mode (one of the few interrupt sources that will) when all internal 
clocks are turned off, this implies that the stimulus to start the DCO 
is derived from the clocking action of combined 'OR'd IRQx sources, 
perhaps as Kris suggests with a bank of 'D' flip flops. Thus the
comment 
regarding MCLK would seem to be self contradictory. However this really 
depends upon the logical processing order within the interrupt logic. If 
  the DCO is started before the actual int flag is latched, and then the 
DCO clock is required to actually latch the int flag, the dependency 
makes some sense, if, however the incoming IRQ signal set the int flag, 
which then causes the DCO to start, the dependency maks no sense.

However, as much as I love to gut things and find out how they work, it 
is often enough to know that they do. Perhaps one day I'll put a micro 
to sleep in LPM4 mode and fire ever faster pulses at it until it doesn't 
wake up. Like the 6us start up, which is, in fact, typically around 
300nsecs, the 1.5MCLKs may be an approximation.

Cheers

Al

On Fri, May 28, 2004 at 01:23:20PM +0930, onestone wrote:
> wake up. Like the 6us start up, which is, in fact,
typically around 
> 300nsecs, the 1.5MCLKs may be an approximation.

I think, they sample the external pins with MCLK (as like other uC's do
this
traditionally) and need one clk-cycle for that (sample at one edges of MCLK
if at the first MCLK edge input is L and at second MCLK edge input is H a
L/H edge is detected). To be sure that your signal is accepted it must be a
little longer as 1 MCLK. Adding some delays -> with 1.5MCLK you are at the
safe side.  But in LPM4 this wouldnt work and they added some logic to wake
up the DCO. This is I would do this and all facts indicates that it is done
this way. I am really interested in your test results (even with LPM3 and
damaged crystal).

        Matthias

Thank all of you for your input regarding this topic.

I am still unsure if using external interrupt to exit low power mode 
is allowed. I now know that it works, (even in LPM4), but I think it 
is a bit by hear say, rather that specification.

By implication slaa139, a TI document, say it is OK. Does TI monitor 
this list and clarify any documention issues?

This is the first time using a TI micro, having been in a different 
camp for 20 years, and I am happy to be corrected in terms of what 
level of information documentation should provide. The 'suck it and 
see' approach seems a little rudimentry - I'd rather read it in the 
specification. 

Regards

David Bagnara

--- In msp430@msp4..., "davidbagnara" <bagnara@o...> wrote:
....
> By implication slaa139, a TI document, say it is
OK. Does TI 
monitor 
> this list and clarify any documention issues?

I used to ask TI's EPIC directly when I had questions like these. 
They always responded very quickly and gave good answers.
I know that at least one of the EPIC guys monitors this list and 
ocasionally posts replies, the last time about a month ago.
So there is hope ;-)

Wolfgang

Matthias Weingart wrote:
> On Fri, May 28, 2004 at 01:23:20PM +0930,
onestone wrote:
> 
>>wake up. Like the 6us start up, which is, in fact, typically around 
>>300nsecs, the 1.5MCLKs may be an approximation.
> 
> 
> I think, they sample the external pins with MCLK (as like other uC's
do this
> traditionally) and need one clk-cycle for that (sample at one edges of MCLK
> if at the first MCLK edge input is L and at second MCLK edge input is H a
> L/H edge is detected). To be sure that your signal is accepted it must be a
> little longer as 1 MCLK. Adding some delays -> with 1.5MCLK you are at
the
> safe side.

The pin logic clearly shows that no clock is involved in the production 
of the internal module IRQx signal, and the fact that in LPM4 the CPU 
and all clocks are turned off enforces this. Thus the pin logic itself 
must be solely responsible for waking up the micro.

   But in LPM4 this wouldnt work and they added some logic to wake
> up the DCO. This is I would do this and all facts
indicates that it is done
> this way. 

The only facts' available are seemingly contradictory ones.

1. The pin logic diagram clearly shows that no clock is used in the 
genertion of the pin IRQ request signal.

2. Practical experience and the user Guide all clearly state that any 
enabled interrupt can wake the processor from LPM4. However, in practice 
one needs to evaluate what this means.

	a. No timer interrupts are valid, the timers are off.
	b. USART interrupts are invalid, the cpu is off as well as the 			timers.
	c. The only functional maskable interrupts are the port pin 			interrupts.
	d. The oscillator fault and Flash violation NMI's are invalid 			since 
the clocks are turned off.
	e. Thus only the external NMI, BOR, POR and port pin interrupts 		are 
available to wake the cpu from LPM4.

3. The User Guide states that port pin signals must be present for 
1.5MCLK periods to be accepted. Since the clock itself is not active it 
cannot be used in the IRQ request signal generation, therefore this 
final 'fact' is either incorrect for the pin interrupts or badly
stated, 
in that the actual clock that is initially started will be the DCO, thus 
  MCLK will default to the DCO. Recovering from a stopped oscillatro 
condition requires the oscillator stability to be established before the 
crystal can be selected as a clock source.


Cheers

Al

> I am really interested in your test results (even
with LPM3 and
> damaged crystal).
> 
>         Matthias
> 
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