Matthias
  I did a redesign for a product that required a 10 year battery life.
An MSP430 was used and because an external, very-low-power comparator
needed a settable reference voltage, four pins of the MSP430 were used
in an R/2R ladder. The comparator's output was tied to an external
interrupt pin on the MSP430 and LPM 4 was used as the idle state.  The
MSP430 was woken up when the comparator tripped.  The project was a
redesign of the California FasTrak "toll tag" and I was told the
production rate was about 200,000+ units per year.  The design was
completed a while back.  Seems to be working OK.

Regards
-Bill Knight
R O SoftWare


On Fri, 28 May 2004 09:39:35 +0200, Matthias Weingart wrote:

>On Fri, May 28, 2004 at 01:23:20PM +0930,
onestone wrote:
>> wake up. Like the 6us start up, which is, in fact, typically around 
>> 300nsecs, the 1.5MCLKs may be an approximation.

>I think, they sample the external pins with MCLK
(as like other uC's do this
>traditionally) and need one clk-cycle for that (sample at one edges of MCLK
>if at the first MCLK edge input is L and at second MCLK edge input is H a
>L/H edge is detected). To be sure that your signal is accepted it must be a
>little longer as 1 MCLK. Adding some delays -> with 1.5MCLK you are at
the
>safe side.  But in LPM4 this wouldnt work and they added some logic to wake
>up the DCO. This is I would do this and all facts indicates that it is done
>this way. I am really interested in your test results (even with LPM3 and
>damaged crystal).

>        Matthias

Hi Al et al,

> The User Guide and individual data sheets are
extremely slack in this 
> area. They display the port pin logic, where it can be clearly seen that 
> the generation of the P1IRQx signal to the interrupt logic is a logic 
> function requiring no clokc, in fact it probably acts as a clock signal 
> itself (being denoted as edge sensitive only, not level sensitive). 
> Unfortunately I have not been able to find a hardware representation of 
> the maskable interrupt logic to establish the exact function beyond this 
> point. Suffice to say that pin interrupts will wake the processor from 
> LPM4 mode (one of the few interrupt sources that will) when all internal 
> clocks are turned off, this implies that the stimulus to start the DCO 
> is derived from the clocking action of combined 'OR'd IRQx
sources, 
> perhaps as Kris suggests with a bank of 'D' flip flops. Thus the
comment 
> regarding MCLK would seem to be self contradictory. However this really 
> depends upon the logical processing order within the interrupt logic. If 
>   the DCO is started before the actual int flag is latched, and then the 
> DCO clock is required to actually latch the int flag, the dependency 
> makes some sense, if, however the incoming IRQ signal set the int flag, 
> which then causes the DCO to start, the dependency maks no sense.

The filter I mentioned using D and JK FFs _needs_ a clock.
It is a synchronous setup, thus the MSP430 couldn't use some such,
as all clocks are completely OFF in our scenario of LPM4.

I agree with Al that the 1.5 X will be an approximation (speculative).
Any FF or logic needs a minimum pulse width for edge_events to qualify,
1.5 times MCLK sounds like a circumstantial and partial account of things.
What freq of MCLK ?
If the core was clocked at 10 kHz, a pulse would need a min. of 150 uS,
which is silly of course, notwithstanding the fact that the clock is OFF in
LPM4 when the actual trigger event happens !

You can't filter an event on a pin with a clock that hasn't started
yet,
whether it takes 6 uS or 600 mS to start up is irrelevant.

-- Kris

Hi Kris,

On Sat, May 29, 2004 at 12:58:40AM +1000, microbit wrote:

> I agree with Al that the 1.5 X will be an
approximation (speculative).
> Any FF or logic needs a minimum pulse width for edge_events to qualify,
> 1.5 times MCLK sounds like a circumstantial and partial account of things.
> What freq of MCLK ?

In this case they would specify some nanoseconds or microseconds. The
dependence from MCLK let me think that there is something clocked in the
circuit between the pins and the flags.

> If the core was clocked at 10 kHz, a pulse would
need a min. of 150 uS,
> which is silly of course, notwithstanding the fact that the clock is OFF in
> LPM4 when the actual trigger event happens !
> 
> You can't filter an event on a pin with a clock that hasn't
started yet,
> whether it takes 6 uS or 600 mS to start up is irrelevant.

The 1.5MCLK means, that there is (hidden in the block diagram) a FF that is
clocked with MCLK and set the INT-flags synced to MCLK to avoid race
conditions. Sound this reasonable?

        Matthias

Hi Matthias,

> > I agree with Al that the 1.5 X will be an
approximation (speculative).
> > Any FF or logic needs a minimum pulse width for edge_events to
qualify,
> > 1.5 times MCLK sounds like a circumstantial and partial account of
things.
> > What freq of MCLK ?
>
> In this case they would specify some nanoseconds or microseconds. The
> dependence from MCLK let me think that there is something clocked in the
> circuit between the pins and the flags.

Correct, unless the context means that it refers to propagation delays
dictated
by the silicon.

 > > If the core was clocked at 10 kHz, a pulse would need a min. of 150
uS,
> > which is silly of course, notwithstanding the
fact that the clock is OFF
in
> > LPM4 when the actual trigger event happens !
> >
> > You can't filter an event on a pin with a clock that hasn't
started yet,
> > whether it takes 6 uS or 600 mS to start up is irrelevant.
>
> The 1.5MCLK means, that there is (hidden in the block diagram) a FF that
is
> clocked with MCLK and set the INT-flags synced to
MCLK to avoid race
> conditions. Sound this reasonable?

It could.
Maybe the simple answer is that the 1.5 MCLK only applies to < LPM4 ?
Like you described, a plausible scenario would be that edge detection is
by XORing input and output of a D Flip Flop, clocked by MCLK.
Maybe in LPM4 this circuit is bypassed, dunno.

You don't need a clocked setup though to select rising or falling edge
on an FF. Self clocking / asynchronous or not, that is the question !

I'd have to look up where the 1.5 times MCLK reference is made in
any case.
Fact remains though that you can wake up the core with those INTs
without clock.

Hi kris,

On Sat, May 29, 2004 at 01:49:34AM +1000, microbit wrote:

> Maybe the simple answer is that the 1.5 MCLK only
applies to < LPM4 ?
> Like you described, a plausible scenario would be that edge detection is
> by XORing input and output of a D Flip Flop, clocked by MCLK.
> Maybe in LPM4 this circuit is bypassed, dunno.

This would be bad for LPM3, when the clock is broken.
I think I should simply try it (when I have the time ;-).

        Matthias

My experience with the MSP430F133 configured in the Active Mode, was
that pulses of 30 nSec duration were recognized as valid Interrupts on
Port 1 pins.
 
  _____  

From: onestone [mailto:onestone@ones...] 
Sent: Friday, May 28, 2004 4:48 AM
To: msp430@msp4...
Subject: Re: [msp430] external interrupt in low power mode
 
Matthias Weingart wrote:
> On Fri, May 28, 2004 at 01:23:20PM +0930, onestone wrote:
> 
>>wake up. Like the 6us start up, which is, in fact, typically around 
>>300nsecs, the 1.5MCLKs may be an approximation.
> 
> 
> I think, they sample the external pins with MCLK (as like other uC's
do this
> traditionally) and need one clk-cycle for that
(sample at one edges of
MCLK
> if at the first MCLK edge input is L and at second
MCLK edge input is
H a
> L/H edge is detected). To be sure that your signal
is accepted it must
be a
> little longer as 1 MCLK. Adding some delays ->
with 1.5MCLK you are at
the
> safe side.

The pin logic clearly shows that no clock is involved in the production 
of the internal module IRQx signal, and the fact that in LPM4 the CPU 
and all clocks are turned off enforces this. Thus the pin logic itself 
must be solely responsible for waking up the micro.

   But in LPM4 this wouldnt work and they added some logic to wake
> up the DCO. This is I would do this and all facts
indicates that it is
done
> this way. 

The only facts' available are seemingly contradictory ones.

1. The pin logic diagram clearly shows that no clock is used in the 
genertion of the pin IRQ request signal.

2. Practical experience and the user Guide all clearly state that any 
enabled interrupt can wake the processor from LPM4. However, in practice

one needs to evaluate what this means.

      a. No timer interrupts are valid, the timers are off.
      b. USART interrupts are invalid, the cpu is off as well as the
timers.
      c. The only functional maskable interrupts are the port pin
interrupts.
      d. The oscillator fault and Flash violation NMI's are invalid
since 
the clocks are turned off.
      e. Thus only the external NMI, BOR, POR and port pin interrupts
are 
available to wake the cpu from LPM4.

3. The User Guide states that port pin signals must be present for 
1.5MCLK periods to be accepted. Since the clock itself is not active it 
cannot be used in the IRQ request signal generation, therefore this 
final 'fact' is either incorrect for the pin interrupts or badly
stated,

in that the actual clock that is initially started will be the DCO, thus

  MCLK will default to the DCO. Recovering from a stopped oscillatro 
condition requires the oscillator stability to be established before the

crystal can be selected as a clock source.


Cheers

Al

> I am really interested in your test results (even
with LPM3 and
> damaged crystal).
> 
>         Matthias
> 
> 
> 
> .
> 
>  
> > . 

Hello all,

Thanks to everyone for their continued input. I appreciate the 
information everyone has provided.

> I'd have to look up where the 1.5 times MCLK
reference is made in
> any case.

The reference is made in slau056d.pdf Section 9.2.5

> Fact remains though that you can wake up the core
with those INTs
> without clock.

A fact or conincidence? Maybe the mask for the next production run 
might alter the characteristics this (highly desirable!) 'feature'.

Regards
David Bagnara

This would seem to confirm that the pin interrupt structure is simply 
logic, with no timing other than normal propagation delays.

Al

Leonard Braun wrote:

> My experience with the MSP430F133 configured in
the Active Mode, was
> that pulses of 30 nSec duration were recognized as valid Interrupts on
> Port 1 pins.
>  
>   _____  
> 
> From: onestone [mailto:onestone@ones...] 
> Sent: Friday, May 28, 2004 4:48 AM
> To: msp430@msp4...
> Subject: Re: [msp430] external interrupt in low power mode
>  
> Matthias Weingart wrote:
> 
>>On Fri, May 28, 2004 at 01:23:20PM +0930, onestone wrote:
>>
>>
>>>wake up. Like the 6us start up, which is, in fact, typically around 
>>>300nsecs, the 1.5MCLKs may be an approximation.
>>
>>
>>I think, they sample the external pins with MCLK (as like other
uC's
> 
> do this
> 
>>traditionally) and need one clk-cycle for that (sample at one edges of
> 
> MCLK
> 
>>if at the first MCLK edge input is L and at second MCLK edge input is
> 
> H a
> 
>>L/H edge is detected). To be sure that your signal is accepted it must
> 
> be a
> 
>>little longer as 1 MCLK. Adding some delays -> with 1.5MCLK you are
at
> 
> the
> 
>>safe side.
> 
> 
> The pin logic clearly shows that no clock is involved in the production 
> of the internal module IRQx signal, and the fact that in LPM4 the CPU 
> and all clocks are turned off enforces this. Thus the pin logic itself 
> must be solely responsible for waking up the micro.
> 
>    But in LPM4 this wouldnt work and they added some logic to wake
> 
>>up the DCO. This is I would do this and all facts indicates that it is
> 
> done
> 
>>this way. 
> 
> 
> The only facts' available are seemingly contradictory ones.
> 
> 1. The pin logic diagram clearly shows that no clock is used in the 
> genertion of the pin IRQ request signal.
> 
> 2. Practical experience and the user Guide all clearly state that any 
> enabled interrupt can wake the processor from LPM4. However, in practice
> 
> one needs to evaluate what this means.
> 
>       a. No timer interrupts are valid, the timers are off.
>       b. USART interrupts are invalid, the cpu is off as well as the
> timers.
>       c. The only functional maskable interrupts are the port pin
> interrupts.
>       d. The oscillator fault and Flash violation NMI's are invalid
> since 
> the clocks are turned off.
>       e. Thus only the external NMI, BOR, POR and port pin interrupts
> are 
> available to wake the cpu from LPM4.
> 
> 3. The User Guide states that port pin signals must be present for 
> 1.5MCLK periods to be accepted. Since the clock itself is not active it 
> cannot be used in the IRQ request signal generation, therefore this 
> final 'fact' is either incorrect for the pin interrupts or badly
stated,
> 
> in that the actual clock that is initially started will be the DCO, thus
> 
>   MCLK will default to the DCO. Recovering from a stopped oscillatro 
> condition requires the oscillator stability to be established before the
> 
> crystal can be selected as a clock source.
> 
> 
> Cheers
> 
> Al
> 
> 
>>I am really interested in your test results (even with LPM3 and
>>damaged crystal).
>>
>>        Matthias
>>
>>
>>
>>.
>>
>> 
>>> . 
> 
> 
> 
> 
> 
> 
> 
> .
> 
>  
> Yahoo! Groups Links
> 
> 
> 
>  
> 
>