Hi!

> r> Using a DC/DC converter is also no option,
because
> r> the overall power consumption must be less than 20uA in order
> r> to get a decent battery life from a 165mAh CR2325 cell.

> look at this DC/DC from TI
> TPS60210,Regulated 3.3-V 100-mA Low-Ripple Charge Pump 
> *UltraLow Operating Current in Snooze Mode, 
> Typical 2 uA with up to 2mA Output Current

Wow. Nice. This would allow to keep the system voltage at
3.3V until the end of battery life. This way I could run the
MSP430 at Vcc/2=1.65V all the time. Could get a little close
to Vpor at low temperature, but will probably be ok.
However, the main problem is that by construction in a watch
battery+ is the real 'ground', case, display, beeper, and 
everything is directly connected to the battery+. 
I would need a 'negative' version of the 60210 to be 
compatible with the watch mainboard. And even then remains
the problem of getting all the capacitors in, even reusing 
the ones that are already there.

But thanks for the suggestion anyway, this TPS60210 is a
very interesting device.

with best regards,
Michael Rothe

Hi!

--- In msp430@y..., "CP" <cp8071@y...> wrote:
> To get that kind of stand-by power I'm
guessing that 
> you're switching the LCD VCC off?

I my first reply I said the display will be on all the time,
but now, after changing to 2M resistors I still measure
about 25uA. 12uA go into the display, 9 uA go into the resistors, 
1uA for the opamp, and 3uA for the 'F149 in LPM3. 
25uA gives only 275 days battery life. Too short.
If I switch off display power, all but the 'F149 is off.
At that rate, the battery would last more than 6 years...
Maybe I should implement a configurable power save option,
something like: display always on between 7am and 11pm
(both times configurable), and in the rest of the time
turn it on at a button press and leave it on for 1 minute 
or so after last button release...
This could bring battery life to well over a year, 
depending on the daily 'on' interval duration, 
without impairing usability too much.

Thanks for the idea!

> This works, but of course if the I/O pin is switched to input
> (display logic 0 output), the I/O sees Vcc/2...
which causes
> the excess current.

There might be a solution for your "inputs at Vcc/2" problem:

I don't know which ports you are using on your F149, but you can 
switch off the input stages of Port P2. The associated register is 
named CAPD.
See MSPx1xx Users Guide (slau049b): "14.3.3 Comparator_A, Port 
Disable Register CAPD" and "14.1.1 Analog Signals at Digital
Inputs".
Search for "CAPD" in the datasheet (slas272c).

The same might be true for P6 (which can be ADC inputs): if you 
switch them to "Module Function" with P6SEL, the input stage should 
be switched off. Didn't check this.
See "input/output schematic" for port P6 on page 64 of the mentioned 
datasheet.


Hope this helps!

Hi!

--- In msp430@y..., "reich_wolfgang" <reich_wolfgang@y...>
wrote:
> I don't know which ports you are using on
your F149, but you can 
> switch off the input stages of Port P2. The associated register is 
> named CAPD... The same might be true for P6...

Thanks for the pointers. Currently I am using P1 for the datalines,
P2.0 for ACLK output, and P4.5 and P4.6 for the control lines.
P1 and the P4 pins were chosen for layout considerations. 
P2 is not available (I need COMP_A), so I will try to use 
P6 instead of P1.

with best regards,
Michael

Hello,

back to basics.

Have you tried to replace the tantalum cap with a ceramic? I tried to peek on my
reference board ('449 and '149) and there're 16V and 10V.. the
first one being a  bit high. 

FYI, these beasts leak - the more the bigger is the difference between the
cap's tolerance and real voltage. Particularly, if you don't need high
accuracy ADC the high capacity cap is an overkill.

greetings,
Matti

-----Alkupernen viesti-----
Lett rothe957 [mailto:rothe@roth...]
Letetty: 30. lokakuuta 2002 11:47

Hi!

--- In msp430@y..., "reich_wolfgang" <reich_wolfgang@y...>
wrote:
> I don't know which ports you are using on
your F149, but you can 
> switch off the input stages of Port P2. The associated register is 
> named CAPD... The same might be true for P6...

Thanks for the pointers. Currently I am using P1 for the datalines,
P2.0 for ACLK output, and P4.5 and P4.6 for the control lines.
P1 and the P4 pins were chosen for layout considerations. 
P2 is not available (I need COMP_A), so I will try to use 
P6 instead of P1.

with best regards,
Michael