Michael Morris (@M65C02A)

Michael has 30+ years of experience in aerospace/defense/commercial electronics. In his career Michael has worked in analog, video, RF, digital electronics and developed software/firmware for embedded processors in Fortran, Pascal, C/C++, Ada, and assembler. Michael has extensive experience with Xilinx FPGAs. As a hobby, Michael enjoys vintage computers and re-implementing classic microcomputers using HDLs and FPGAs.

Use DPLL to Lock Digital Oscillator to 1PPS Signal

Michael Morris July 24, 20168 comments

There are occasions where it is desirable to lock a digital oscillator to an external time reference such as the 1PPS (One Pulse Per Second) signal output from a GPS receiver. One approach would be to synchronize a fixed frequency oscillator on the leading edge of the 1PPS signal. In many cases, this will result in adequate performance. However, in situations where simple synchronization does not provide adequate performance, digital phase-lock techniques can be applied to a...

Fit Sixteen (or more) Asynchronous Serial Receivers into the Area of a Standard UART Receiver

Michael Morris March 29, 20155 comments

This article will describe a technique, available in many current FPGA architectures, to fit a large amount of logic into a small area. About ten years ago now (Feb/Mar 2005), I helped develop a multi-line Caller ID product. The Multi-Channel Asynchronous Receiver (MCAR) FPGA core developed for that product will be used to illustrate the technique(s) needed to fit a 16 channel MCAR into a single Spartan II XC2S30-5VQ100 FPGA.

To stay true to the original design, I...

Use Microprogramming to Save Resources and Increase Functionality

Michael Morris March 21, 2015

Microprogramming is a design approach that every FPGA designer should have in their bag of tricks. I subscribe to the concept that microprogramming is a structured approach to the design of state machines. This is essentially the view of Maurice Wilkes when he first proposed microprogramming in 1951 as an alternative method for the implementation of the control section of a computer. Wilkes was interested in improving the reliability and reducing time needed to implement...

Re: Formal Verification of Software

Reply posted 3 years ago (07/26/2021)
That’s too bad you weren’t able to use it, but glad that you were successful

Re: Formal Verification of Software

Reply posted 3 years ago (07/23/2021)

Re: Why CRC with EPROM?

Reply posted 3 years ago (06/26/2021)
Another approach with similar error detection capabilities to CRCs, but which doesn't require bit-level manipulations and bit shifting, is the Fletcher's Checksum.I've...

Re: Design of the A/D converter driver interface

Reply posted 4 years ago (01/08/2021)
Your defined interface appears to cover most of the bases. However, to answer your question regarding whether your driver definition is appropriate or not, you...

Re: extended memory move operations in 8051

Reply posted 5 years ago (03/25/2019)
To the best of my recollection, your comments accurately describe what the code snippets will do.MOVX A,@DPTR will only temporarily affect the upper address bus...

Re: Preventing Forum Fatigue

Reply posted 5 years ago (01/18/2019)
This situation occasionally occurs on all forums like this one. Helpful suggestions encourage additional questions.I don't think that a blanket policy like that...

Re: AMD 188 understanding with EEPROM

Reply posted 7 years ago (06/16/2017)
Generally, the AMD 188 processors, the Am188ER and Am188ES, have two chip select outputs, nUMCS and nLMCS, which split the 1MB address space in half on reset and...

Re: BusOff state question

Reply posted 7 years ago (05/10/2017)
IOWs, are you using DeviceNet, CAN-Open, CAN Kingdom, or any such higher level protocol?BTW. what CAN transceiver does your implementation use?

Re: BusOff state question

Reply posted 7 years ago (05/10/2017)
I can't say that we'll be able help solve your problem, or even suggest a reasonable path to diagnosing the problem described. However, I think that you need to...

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