extended memory move operations in 8051Started by 4 years ago●7 replies●latest reply 4 years ago●208 views
I'm trying to figure out the best way to access continuous data from different parts of memory.
Here's a sample of my 8051 code:
;Set DPTR to 5678h ;and other DPTR via P2:R0 to 1234h ;We want two bytes of data from 1234h to 1235h ;and two bytes from 5678h to 5679h mov P2,#12h mov R0,#34h mov DPH,#56h mov DPL,#78h movx A,@DPTR ;Get data from address 5678h inc DPTR movx A,@DPTR ;Get data from address 5679h movx A,@R0 ;Get data from 1234h? inc R0 movx A,@R0 ;Get data from 1235h?
If I used the above code, would my logic in the comments make sense, or would any movx with the @dptr in it override the value of P2 permanently (to the point where I always have to update it every time I use movx with @r0 in it)?
Since you still want to use an 8051 instead of an ARM Cortex-M like most people would do, you should consider downloading an 8051 simulator such as "EdSim51DI" and you will have the answer to your question in a few minutes.
I'm using an AT89S52, and I can also use AT89LP52 and AT89S8253.
The primary reason is price. Also I know much of the assembly in the 8051 and I get more control of the processor when I use it.
Yes I understand it takes longer and its more time consuming, but I'm sure people who make C compilers will write code that converts C code to assembly code.
I had a quick look on Mouser,
100 off AT89LP52 = £0.771 ("20HHz", 0.25kRAM, 8k flash)
100 off STM32L010K4T6 = £0.64 (32MHz Cortex M0, 2K ram, 16k flash)
The ancient 8051 technology is no cheaper in simple price comparison and in terms of performance / cost it's truly dreadful.
Move into the 21st century, use a decent processor and code it in C, there is a reason that most of us do this !
To the best of my recollection, your comments accurately describe what the code snippets will do.
MOVX A,@DPTR will only temporarily affect the upper address bus lines on P2. Once that cycle is complete, the P2 lines will return to whatever levels you have programmed into the P2 port latch.
I have not actively used one of these processor in roughly 20 years, although when I used it, it was attached directly to my brain stem. ;)
Curiosity, why are you using the 80C51? I would second Mark's recommendation the the ARM microcontrollers for any new designs. If I did not need to use an 8051 today because of a legacy product, I would using a similar ARM to the one he recommends.
And I add : Why are you using assembly language?
The port 0 and port 2 in intel 8051 is designed such that depending on the instruction executed the address / data transaction occur. I have enclosed the architecture diagram from a MCS 51 equivalent datasheet, port 0 and 2 schematics and external memory read / write cycle from original intel 8051 data sheet.
According to this data sheet info:
during MOVX A,@DPTR, DPTR data will be latched to address and during MOVX A,@R0, P2 and R0 will be latched into the address.
It would not change P2 / P0 address to DPTR permanently.