On Feb 20, 11:24 am, "Didi" <d...@tgi-sci.com> wrote:> > You top posted and left out the important number: 80 MHz. > > I did not leave anything out. > I just put it in the complete context I quoted > at a place which apparently did not please you which is > essentially your problem.I did not invent this format, just follow it.> > I did post what I deemed relevant - the OP knew, as he had > indicated, that CPLD was an obvious option. My suggestion > may or may not have been obvious to him, it was informative > in the context without restating what he obviously knew.You knew, he knew and I knew, but hundreds of other readers might not know.> > But why bother about contents when we can concentrate > on vital issues like top, bottom etc. posting religions.It's public manners and simple considerations for other readers. I "top post" in emails, but "content post" in newsgroups.
80MHz clock, discrete logic
Started by ●February 20, 2007
Reply by ●February 20, 20072007-02-20
Reply by ●February 20, 20072007-02-20
Steve at fivetrees wrote:> "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message > news:45db4513$1@clear.net.nz... > >>Steve at fivetrees wrote: >> >> >>>Linnix: any particular CPLD family? I'm a CPLD virgin (although I have >>>designed ASICs, about 20 years back...). >> >>What supply voltage(s) do you have ? > > > The circuit is for clock recovery of a 10MHz NRZ serial stream at TTL levels > (i.e. 0-5V).if you need to power this from 5V, and accept 5V CMOS drive, that will move you back a generation - the ones I quoted are 1.8V cores 3.3V IO, tho lattice MACH4000 claim 5V tolerance, provided it is not on too many pins... 80Mhz is going to need some of the faster 5V parts. XC9536 in faster speed grades is one option. Expect around 60mA Icc Altera also have some older/higher power 5V CPLDs. -jg
Reply by ●February 20, 20072007-02-20
> You knew, he knew and I knew, but hundreds of other readers might not > know.I agree with that, although he had mentioned it already in his first message.> It's public manners and simple considerations for other readers. > I "top post" in emails, but "content post" in newsgroups.And I happen to think that combining the good parts of both top and bottom posting is the best practice nowadays. You objected to my omission of the "80 MHz" in my top-quoted part, perhaps you forgot to look at the subject line. Dimiter On Feb 20, 10:10 pm, "linnix" <m...@linnix.info-for.us> wrote:> On Feb 20, 11:24 am, "Didi" <d...@tgi-sci.com> wrote: > > > > You top posted and left out the important number: 80 MHz. > > > I did not leave anything out. > > I just put it in the complete context I quoted > > at a place which apparently did not please you which is > > essentially your problem. > > I did not invent this format, just follow it. > > > > > I did post what I deemed relevant - the OP knew, as he had > > indicated, that CPLD was an obvious option. My suggestion > > may or may not have been obvious to him, it was informative > > in the context without restating what he obviously knew. > > You knew, he knew and I knew, but hundreds of other readers might not > know. > > > > > But why bother about contents when we can concentrate > > on vital issues like top, bottom etc. posting religions. > > It's public manners and simple considerations for other readers. > I "top post" in emails, but "content post" in newsgroups.
Reply by ●February 20, 20072007-02-20
"Roberto Waltman" <usenet@rwaltman.net> wrote in message news:dmfmt25l4stfcqm6441m7q5i142d4qtb5u@4ax.com...> "linnix" <me@linnix.info-for.us> wrote: > > ... > >More of a reason to use a single chip CPLD. > >Easy to find 200 to 300 MHz chips. > > > > > The original description of a "simple synchronous logic circuit, using > a handful of flipflops and gates" does indeed suggest using a CPLD, > but for the sake of completeness, it may be possible to simulate that > logic in software. There are several small processors approaching or > passing the 100 Mips mark.Absolutely not. A 100Mips processor can only do one step in 10ns. That means that any output is at least 20ns lagging on an input. (read input, set output, two instructions). Compare that to the propagation delay of 125MHz logic, which is in the order of 4 ns. Meindert
Reply by ●February 20, 20072007-02-20
On Feb 20, 12:55 pm, "Meindert Sprang" <m...@NOJUNKcustomORSPAMware.nl> wrote:> "Roberto Waltman" <use...@rwaltman.net> wrote in message > > news:dmfmt25l4stfcqm6441m7q5i142d4qtb5u@4ax.com... > > > "linnix" <m...@linnix.info-for.us> wrote: > > > ... > > >More of a reason to use a single chip CPLD. > > >Easy to find 200 to 300 MHz chips. > > > The original description of a "simple synchronous logic circuit, using > > a handful of flipflops and gates" does indeed suggest using a CPLD, > > but for the sake of completeness, it may be possible to simulate that > > logic in software. There are several small processors approaching or > > passing the 100 Mips mark. >That would cost at least 100 dollars, compared to a 2 dollars CPLD.> Absolutely not. A 100Mips processor can only do one step in 10ns. That means > that any output is at least 20ns lagging on an input. (read input, set > output, two instructions).Not too mention branchings as well.> Compare that to the propagation delay of 125MHz > logic, which is in the order of 4 ns. > > Meindert
Reply by ●February 20, 20072007-02-20
Steve at fivetrees wrote:> > The circuit is for clock recovery of a 10MHz NRZ serial stream at TTL levels > (i.e. 0-5V).Another thought - if this is simple, don't exclude the venerable 22V10, the lattice ispGAL22V10A series has the MHz, and 5V compliance with 3.3V Vcc. -jg
Reply by ●February 21, 20072007-02-21
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:45db9c57$1@clear.net.nz...> Steve at fivetrees wrote: >> >> The circuit is for clock recovery of a 10MHz NRZ serial stream at TTL >> levels (i.e. 0-5V). > > Another thought - if this is simple, don't exclude the venerable > 22V10, > the lattice ispGAL22V10A series has the MHz, and 5V compliance > with 3.3V Vcc. > > -jgI was going to suggest the 22V10 as well but a quick google produced one that wasn't quick enough. Jim has found one though, so this could be a good route - I know of quite a few people who cut their teeth on the 22V10 because it is nice a simple to work with.
Reply by ●February 21, 20072007-02-21
Tom Lucas wrote:> "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message > news:45db9c57$1@clear.net.nz... > >>Steve at fivetrees wrote: >> >>>The circuit is for clock recovery of a 10MHz NRZ serial stream at TTL >>>levels (i.e. 0-5V). >> >>Another thought - if this is simple, don't exclude the venerable >>22V10, >>the lattice ispGAL22V10A series has the MHz, and 5V compliance >>with 3.3V Vcc. >> >>-jg > > > I was going to suggest the 22V10 as well but a quick google produced one > that wasn't quick enough. Jim has found one though, so this could be a > good route - I know of quite a few people who cut their teeth on the > 22V10 because it is nice a simple to work with.There are more than I thought, with 5V Vcc : most 100+MHz, so not as quick as the lattice one, but still fine for 80MHz Atmel ATF22V10C - down to 5ns, 10ns and below look OK for 80MHz Atmel ATF750C - Two 22V10s in one package, 7ns variant, multiple clocks ICT/Anachip PEEL22CV10 - down to 7ns and ATF1502AS is a 5V part, that has a 10ns/7ns variants -jg
Reply by ●February 22, 20072007-02-22
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:45dc1a0e$1@clear.net.nz...> Tom Lucas wrote: >> "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message >> news:45db9c57$1@clear.net.nz... >> >>>Steve at fivetrees wrote: >>> >>>>The circuit is for clock recovery of a 10MHz NRZ serial stream at TTL >>>>levels (i.e. 0-5V). >>> >>>Another thought - if this is simple, don't exclude the venerable 22V10, >>>the lattice ispGAL22V10A series has the MHz, and 5V compliance >>>with 3.3V Vcc. >>> >>>-jg >> >> I was going to suggest the 22V10 as well but a quick google produced one >> that wasn't quick enough. Jim has found one though, so this could be a >> good route - I know of quite a few people who cut their teeth on the >> 22V10 because it is nice a simple to work with. > > There are more than I thought, with 5V Vcc : most 100+MHz, so not as quick > as the lattice one, but still fine for 80MHz > > Atmel ATF22V10C - down to 5ns, 10ns and below look OK for 80MHz > > Atmel ATF750C - Two 22V10s in one package, 7ns variant, multiple clocks > > ICT/Anachip PEEL22CV10 - down to 7ns > > and ATF1502AS is a 5V part, that has a 10ns/7ns variantsThanks, guys. I'm very grateful for the leg-up. I'll let you know how I get on. Steve http://www.fivetrees.com
Reply by ●February 23, 20072007-02-23
On Feb 20, 3:13 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote:> Steve at fivetrees wrote: > > "Jim Granville" <no.s...@designtools.maps.co.nz> wrote in message > >news:45db4513$1@clear.net.nz... > > >>Steve at fivetrees wrote: > > >>>Linnix: any particular CPLD family? I'm a CPLD virgin (although I have > >>>designed ASICs, about 20 years back...). > > >>What supply voltage(s) do you have ? > > > The circuit is for clock recovery of a 10MHz NRZ serial stream at TTL levels > > (i.e. 0-5V). > > if you need to power this from 5V, and accept 5V CMOS drive, that > will move you back a generation - the ones I quoted are 1.8V cores > 3.3V IO, tho lattice MACH4000 claim 5V tolerance, provided it is not > on too many pins... > > 80Mhz is going to need some of the faster 5V parts. > XC9536 in faster speed grades is one option. > Expect around 60mA Icc > > Altera also have some older/higher power 5V CPLDs. > > -jgThe Xilinx XC9500XL series CPLDs run on 3.3 volts and has 5 volt tolerant inputs. HTH -Dave Pollum
