80MHz clock, discrete logic

On Feb 20, 2:07 pm, "Steve at fivetrees" <s...@NOSPAMTAfivetrees.com>
wrote:
> "Jim Granville" <no.s...@designtools.maps.co.nz> wrote in message
>
> news:45db4513$1@clear.net.nz...
>
> > Steve at fivetrees wrote:
>
> >> Linnix: any particular CPLD family? I'm a CPLD virgin (although I have
> >> designed ASICs, about 20 years back...).
>
> > What supply voltage(s) do you have ?
>
> The circuit is for clock recovery of a 10MHz NRZ serial stream at TTL levels
> (i.e. 0-5V).
>
I did something like that.  The data rate was 2.5 Mb/s NRZ and I had
to convert it into something similar to Manchester.  I breadboarded it
using a XC9572.  I wire-wrapped it on a proto board that had a plane
on each side.  It worked great.

> > Present fast/Low power CPLD Candiates are :
>
> <snip>
>
> Superb. And thanks to linnix too.
>
> /me goes off to do some reading
>
> Stevehttp://www.fivetrees.com

-Dave Pollum
(I'm between jobs (rif'd) so if I can help let me know.)