Tilera to Introduce 64-Core Processor

In article <YiOPi.1158$uC1.469@trnddc04>, w.newell@TAKEOUTverizon.net 
says...
> On Fri, 12 Oct 2007 16:16:32 +0000, The little lost angel wrote:
> 
> > I'm a bit puzzled by this. If the cores are laid out in a checkerboard
> > like grid, doesn't that mean each core is linked to the 8 cores around
> > it? So it would still come up to some kind of latency bottleneck
> > wouldn't it? What difference is it from AMD's ccHTT links except
> > they've got a few more?
> > 
> A cpu has more than one layer. I'm not sure how many it has but I think
> AMD's is about 9 layers with the K8. I'd suspect the tile64 is a lot more.
> The interconnect would be similar to AMD's HT interconnect bus.

The PowerPC 970MP was ten layers.  The bad news is that you need them 
for things other than interconnecting cores.  The same thing that's 
forcing more cores (because we have nothing better to do with 
transistors) is forcing more layers of interconnect, just to wire 
them all up.

> > Or does he mean the 64 cores are all directly connected to each other...
> > meaning there are some 63 connections coming out of each core to every
> > other core for some mindboggling number? (I think 63+62+61+... but my
> > abysmal ability with maths fails me here) But essentially becoming a
> > nightmare if the number of cores go out. So unlikely to be case, no?
> 
> Probably the reason the core speeds are kept a lot lower. I know I'd like
> to have one of these on a small MB compatable with an ATX/BTX case, but
> realisitically, I have no need for so much power. But cutting electrical
> use would be nice.

Cores speeds are likely lower so it can be cooled.

-- 
  Keith

On Thu, 11 Oct 2007 11:02:14 -0700, AirRaid wrote:

> Tilera expects to sell the TILE64 processor for $435 in lots of 10,000
> units. The company is also planning a 36-core and 120-core processor for
> the near future.

Shucks, soon we won't bother with putting memory in systems
anymore, we'll just have whole CPU cores where individual memory
bits used to be :-).

krw wrote:

>Cores speeds are likely lower so it can be cooled.

More likely they are using older fabrication technology 
with larger hfeatures and running it as fast as it will go.

-- 
Guy Macon
<http://www.guymacon.com/>

On Fri, 12 Oct 2007 17:48:26 -0400, krw <krw@att.bizzzz> wrote:

>The PowerPC 970MP was ten layers.  The bad news is that you need them 
>for things other than interconnecting cores.  The same thing that's 
>forcing more cores (because we have nothing better to do with 
>transistors) is forcing more layers of interconnect, just to wire 
>them all up.

So it'll just be a real mess isn't it? And they can't just make more
cores using the same blue print can they? Since changing the design
from 64 core to say 128 core would require a whole new design with
like double the number of interconnects no?

Or are they actually just saying every core is identical and only
directly connected to their immediate neighbours? Since this seems to
be the logical way to me.

>Cores speeds are likely lower so it can be cooled.

Wouldn't this be like getting close to the same problem as whowasit's
parallel hz idea? Seems to me like this 64core thingy is only going to
be good for certain problems since most stuff just isn't going to be
really parallelizable to such an extent. While many things will just
suffer from the low clockspeed/high latency. In other words, not going
to be a mass market product?

-- 
A Lost Angel, fallen from heaven 
Lost in dreams, Lost in aspirations, 
Lost to the world, Lost to myself

On Oct 12, 9:16 am, a?n?g?...@lovergirl.lrigrevol.moc.com (The little
lost angel) wrote:
> On Thu, 11 Oct 2007 11:02:14 -0700, AirRaid <AirRaid...@gmail.com>
> wrote:
>
> >Tilera to Introduce 64-Core Processor
> >By Andy Patrizio
>
> >"The real problem with scale is existing multi-core architectures use
> >a bus. In that architecture, the bus is a central switch and all the
> >cores are connected to the single central switch. A packet has to go
> >through it no matter what, which is fine for one, two or four cores,
> >but it does not scale," he told internetnews.com.
>
> >Tilera uses a mesh architecture, where the cores are laid out in a
> >checkerboard-like grid, all connected through high-speed
> >interconnects. "In architectures of this sort, you can keep growing
> >and you won't have any serious congestion," said Agarwal.
>
> I'm a bit puzzled by this. If the cores are laid out in a checkerboard
> like grid, doesn't that mean each core is linked to the 8 cores around
> it?

Reading between the lines, it's probably a torus rather than a mesh.
An 8x8 2D torus and a 4x4x4 3D torus would give a maximum of 8 hops
and 6 hops, respectively, between cores. That doesn't even take into
account the latency to RAM. This processor would probably work well
only on dataflow problems (which access RAM very little).

> So it would still come up to some kind of latency bottleneck
> wouldn't it? What difference is it from AMD's ccHTT links except
> they've got a few more?

A heck of a lot more hops and so, potentially, a much higher latency.
On the other hand, on chip links can be made wider - perhaps even 8
times the width of HTT links thereby cutting latency per link.

> Or does he mean the 64 cores are all directly connected to each
> other.

No, since a mesh is mentioned.

On Oct 11, 4:45 pm, "Michael N. Moran" <mnmo...@bellsouth.net> wrote:
> AirRaid wrote:
> > Tilera to Introduce 64-Core Processor
> > By Andy Patrizio
>
> Oh great ... more marketing hyperbole spam from AirRaid.

nice attempt at trolling.

In comp.sys.ibm.pc.hardware.chips krw <krw@att.bizzzz> wrote in part:
> In article <YiOPi.1158$uC1.469@trnddc04>, w.newell@TAKEOUTverizon.net 
>> On Fri, 12 Oct 2007 16:16:32 +0000, The little lost angel wrote:
>> > I'm a bit puzzled by this. If the cores are laid out in a
>> > checkerboard like grid, doesn't that mean each core is linked
>> > to the 8 cores around it? So it would still come up to some
>> > kind of latency bottleneck wouldn't it? What difference is
>> > it from AMD's ccHTT links except they've got a few more?

>> A cpu has more than one layer. I'm not sure how many it has but I think
>> AMD's is about 9 layers with the K8. I'd suspect the tile64 is a lot more.
>> The interconnect would be similar to AMD's HT interconnect bus.
> 
> The PowerPC 970MP was ten layers.  The bad news is that you
> need them for things other than interconnecting cores.  The same
> thing that's forcing more cores (because we have nothing better
> to do with transistors) is forcing more layers of interconnect,
> just to wire them all up.

Like L'Angel, I'm a bit puzzled, but in a different direction:
Lay the cores out in a flat checkerboard.  Bus each row together
to a shared x8 section of L2 cache.  One/two layers max.  Those
cores better each have their own L1s!

>> Probably the reason the core speeds are kept a lot lower. I
>> know I'd like to have one of these on a small MB compatable
>> with an ATX/BTX case, but realisitically, I have no need
>> for so much power. But cutting electrical use would be nice.
> 
> Cores speeds are likely lower so it can be cooled.

And power/gd current handled.  Also to avoid overloading
L2 and main RAM busses.

-- Robert

I wondering that have 64 cores in a one CPU.But which programming
langs can be solved parallel's problem?C++,Java or Fortress?

>> Tilera expects to sell the TILE64 processor for $435 in lots of 10,000
>> units. The company is also planning a 36-core and 120-core processor for
>> the near future.

>Shucks, soon we won't bother with putting memory in systems
>anymore, we'll just have whole CPU cores where individual memory
>bits used to be :-).

That's the point where it becomes interesting. Having only a few of some 
resource makes it hard to manage. Having one is easy - there's no choice. 
having lots is easy - use what you can. Having a few means you have to 
choose carefully.

For most programs, the best way to use two cores is to turn one off. With 
64 you can start running pipelines and arrays, which is what the Tilera 
looks like it was designed for.




-- 
	mac the na�f

>Or are they actually just saying every core is identical and only
>directly connected to their immediate neighbours? Since this seems to
>be the logical way to me.

it's a grid, where each processor has 4 neighbors. See
	http://www.tilera.com/pdf/ArchBrief_Arch_V1_Web.pdf

>Wouldn't this be like getting close to the same problem as whowasit's
>parallel hz idea? Seems to me like this 64core thingy is only going to
>be good for certain problems since most stuff just isn't going to be
>really parallelizable to such an extent. While many things will just
>suffer from the low clockspeed/high latency. In other words, not going
>to be a mass market product?

Of course not - it doesn't run Office 97, so it's not a general-purpose
CPU. they're going for the embedded market, which is much larger, but
populated largely by 8-bit CPUs, battery-power ARMs, DSPs, FPGAs.

Perhaps it'll find use as a game platform, set-top box, speech recognizer,
packet sniffer.
-- 
	mac the na�f