Tilera to Introduce 64-Core Processor

Wes Newell wrote:
>
>Qu0ll wrote:
>
>> "AirRaid" <AirRaidJet@gmail.com> wrote in message 
>> news:1192125734.851641.264020@v3g2000hsg.googlegroups.com...
>> 
>>> Tilera to Introduce 64-Core Processor
>> 
>> Is it YAXP (Yet Another X86 Processor) or is it introducing a new 
>> instruction set?
>
>It's a new cpu. Right now only supported with Linux. Which is fine with
>me. I don't use Microsloth anyway.

It seems strange to me that they say the following things:

[1] It runs Linux.

[2] It has a new instruction set and architecture

[3] The C/C++ compiler is still in the future.

What's wrong with this picture?

-- 
Guy Macon
<http://www.guymacon.com/>

Guy Macon wrote:
> It seems strange to me that they say the following things:
> 
> [1] It runs Linux.
> 
> [2] It has a new instruction set and architecture
> 
> [3] The C/C++ compiler is still in the future.
> 
> What's wrong with this picture?

My guess is that they've ported the gcc backend to make code for a 
single core, which is enough to boot Linux on it, then they have some 
asm snippets to run demos (Mandelbrot sets anyone?) across all 64.

Terje

-- 
- <Terje.Mathisen@hda.hydro.com>
"almost all programming can be viewed as an exercise in caching"

I find all of the discussions interesting; most of them were analogous to 
the ones we had in the 80's when DARPA sponsored the Supercomputing Program. 
A number of multiprocessor chips were built and used to implement massively 
parallel computers.  An example of which, was the Thinking Machines 64,000 
processor computer, which was later extended beyond 64K processors. 
Communications between processors and fast memory accessibility to all the 
processors was and still is the problem with massively parallel computers. 
It became obvious that these computers were very useful for specific types 
of problems which fit their architectures.  They ended up not being very 
useful as general purpose machines, unless you were running many 
simultaneous applications and even then they usually were not cost 
effective.  Don't get me wrong they were very cost effective for some very 
specific problems.

There is not enough information in this article to show me that they have 
come up with a substantially better solution to the high speed general 
purpose computing problem in a cost effective manner.  If anything, the 
market they are going after coincides with the ones that the 80's machines 
were useful in.

Regards

John




"AirRaid" <AirRaidJet@gmail.com> wrote in message 
news:1192125734.851641.264020@v3g2000hsg.googlegroups.com...
> Tilera to Introduce 64-Core Processor
> By Andy Patrizio
>
> An MIT-inspired startup will introduce a new multi-core chip today at
> the annual Hot Chips conference at Stanford University. The TILE64
> boasts a "clean sheet" design, unencumbered by any legacy
> compatibility concerns, that Tilera says will provide a huge leap in
> multithreaded performance.
>
> Tilera was founded in 2004 to bring to market the multi-core processor
> designs of MIT researcher Anant Agarwal. Agarwal created what he
> called a "mesh" multi-core architecture, where the cores are all
> interconnected rather than going through a frontside bus, as Intel's
> multi-core chips do.
>
> Agarwal first created this multi-core architecture in 1996, long
> before Intel and AMD were anywhere close to doing it. The project
> received funding from the Defense Advanced Research Project Agency
> (DARPA) and the National Science Foundation, the agency that managed
> the Internet for decades.
>
> Tilera holds 40-plus patents for its multi-core design. TIL64 will be
> the first in a series of processors built around massively multi-core
> chips. The TILE64 processor contains 64 full-featured, programmable
> cores that Tilera claims can perform 500 billion operations per second
> and delivers ten times the performance and thirty times the
> performance-per-watt of the Intel dual-core Xeon.
>
> Agarwal said the company can make these performance leaps because it
> doesn't use any legacy technologies or designs.
>
> "The real problem with scale is existing multi-core architectures use
> a bus. In that architecture, the bus is a central switch and all the
> cores are connected to the single central switch. A packet has to go
> through it no matter what, which is fine for one, two or four cores,
> but it does not scale," he told internetnews.com.
>
> Tilera uses a mesh architecture, where the cores are laid out in a
> checkerboard-like grid, all connected through high-speed
> interconnects. "In architectures of this sort, you can keep growing
> and you won't have any serious congestion," said Agarwal.
>
> Intel has promised to dispense with the frontside bus with the Nehalem
> architecture, due late next year. AMD does not have a frontside bus in
> the Opteron, but it's also using four cores at the most, while Tilera
> is at 64.
>
> The TILE family can scale up to even more, or down to a two-core
> design for the smallest of designs, such as a cell phone. Its power
> consumption is a few hundred milliwatts per core, Agarwal said. Its
> clock speed will range from 600MHz to 1GHz.
>
> But there's a lot more on the chip than just cores. It has a pair of
> 10 gigabit Ethernet ports directly on the chip for high speed
> networking, as well as on-board I/O and peripheral controllers. Its
> integrated memory controllers allow for up to 200 gigabits of memory
> bandwidth within the chip.
>
> That's what made the TILE64 chip so appealing to Top Layer, developer
> of network security and intrusion detection appliance. The company had
> built its own processors but now plans to switch to Tilera's chips,
> according to Chief Strategy Officer Mike Paquette.
>
> "Our software is a multi-core design, and we were able to map out
> functionality almost 1 for 1 for each process to a core in a Tilera
> chip," he said. "The performance we expect in our estimates exceeds
> what we could have gotten from any silicon providers."
>
> Top Layer decided to license processors for future products rather
> than the expense of building any more, and no other processors had the
> scalability. "Because the movement of data is so much of what we do,
> we needed a multi-core chip that was optimized for what we were doing
> rather than something optimized for general purpose computing Tilera
> has capabilities for network capabilities that are far ahead of what
> you can get from [x86] processors," said Paquette.
>
> Tilera will ship a full development toolkit, called the Multicore
> Development Environment (MDE), for building applications. It's an
> Eclipse-based Integrated Development Environment (IDE) with an ANSI
> standard C compiler, an application level library and tools for
> debugging and profiling multi-core processors.
>
> Wisely, Tilera is not taking on Intel and AMD right out of the gate,
> as Transmeta did. It's going for the embedded market.
>
> "We're focused on embedded because we are a startup and want to go
> into a space where there is massive demand for performance like ours.
> We can focus on a couple of markets and do really well in those
> markets by addressing customer demands squarely and don't have to go
> up against a dominant competitor," said Agarwal.
>
> Tilera expects to sell the TILE64 processor for $435 in lots of 10,000
> units. The company is also planning a 36-core and 120-core processor
> for the near future.
>
>
> http://www.internetnews.com/ent-news/article.php/3695116
> 

On Sun, 14 Oct 2007 13:14:30 +0000, Guy Macon wrote:

> 
> 
> 
> Wes Newell wrote:
>>
>>Qu0ll wrote:
>>
>>> "AirRaid" <AirRaidJet@gmail.com> wrote in message 
>>> news:1192125734.851641.264020@v3g2000hsg.googlegroups.com...
>>> 
>>>> Tilera to Introduce 64-Core Processor
>>> 
>>> Is it YAXP (Yet Another X86 Processor) or is it introducing a new 
>>> instruction set?
>>
>>It's a new cpu. Right now only supported with Linux. Which is fine with
>>me. I don't use Microsloth anyway.
> 
> It seems strange to me that they say the following things:
> 
> [1] It runs Linux.
> 
> [2] It has a new instruction set and architecture
> 
> [3] The C/C++ compiler is still in the future.
> 
> What's wrong with this picture?

[3] is not correct. There is a C compiler for it, just not a C++ compiler.

http://www.tilera.com/products/software.php

-- 
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Wes Newell wrote:

>There is a C compiler for it, just not a C++ compiler.
>
>http://www.tilera.com/products/software.php

Ah.  My mistake.  Sorry for the error, and thanks for the correction.

In comp.sys.ibm.pc.hardware.chips krw <krw@att.bizzzz> wrote in part:
> My point was that as transistors get smaller, more layers
> are needed simply to support the local interconnect.  We were
> at ten layers three years ago.  More doesn't come cheap.

A good point, but I wonder if those extra layers are
instrinsically necessary, or a result of trying to alleviate
timing problems from pushing clock.  As you point out, heavy
MP could not push clock.

> One layer doesn't do much since you don't get to put
> resistors on top to jump over wires.  ;-) Two aren't going
> to support much density of wiring either.

Sorry.  I guess you count insulating layers on chips,
unlike PCBs.  

> Yes, and think about the number of L2 ports needed. <shudder>

Maybe not.  Just bus access by row and separate L2s for each row.
Let MOESI snooping pick it up.

-- Robert

"Robert Redelmeier" <redelm@ev1.net.invalid> wrote in message 
news:bCvQi.5389$y21.2318@newssvr19.news.prodigy.net...
> In comp.sys.ibm.pc.hardware.chips krw <krw@att.bizzzz> wrote in part:
>> My point was that as transistors get smaller, more layers
>> are needed simply to support the local interconnect.  We were
>> at ten layers three years ago.  More doesn't come cheap.
>
> A good point, but I wonder if those extra layers are
> instrinsically necessary, or a result of trying to alleviate
> timing problems from pushing clock.  As you point out, heavy
> MP could not push clock.
>
>> One layer doesn't do much since you don't get to put
>> resistors on top to jump over wires.  ;-) Two aren't going
>> to support much density of wiring either.
>
> Sorry.  I guess you count insulating layers on chips,
> unlike PCBs.
>
>> Yes, and think about the number of L2 ports needed. <shudder>
>
> Maybe not.  Just bus access by row and separate L2s for each row.
> Let MOESI snooping pick it up.
>
> -- Robert
>
>
I think current state of art processes are at or above 10 levels of 
metal, plus insulator and vias. 

In article <bCvQi.5389$y21.2318@newssvr19.news.prodigy.net>, 
redelm@ev1.net.invalid says...
> In comp.sys.ibm.pc.hardware.chips krw <krw@att.bizzzz> wrote in part:
> > My point was that as transistors get smaller, more layers
> > are needed simply to support the local interconnect.  We were
> > at ten layers three years ago.  More doesn't come cheap.
> 
> A good point, but I wonder if those extra layers are
> instrinsically necessary, or a result of trying to alleviate
> timing problems from pushing clock.  As you point out, heavy
> MP could not push clock.
>
The layers are necessary because the transistors are more densely 
packed than wires can be.  Wires don't scale like silicon.  Copper 
helped quite a bit, but there is nowhere to go from there.

> > One layer doesn't do much since you don't get to put
> > resistors on top to jump over wires.  ;-) Two aren't going
> > to support much density of wiring either.
> 
> Sorry.  I guess you count insulating layers on chips,
> unlike PCBs.  

No, just counting metal.  Wires can't be infinitely thin, nor with a 
zero pitch.  

> > Yes, and think about the number of L2 ports needed. <shudder>
> 
> Maybe not.  Just bus access by row and separate L2s for each row.
> Let MOESI snooping pick it up.

You'd still have at least 18 ports to each L2. <yikes!>


-- 
  Keith

krw wrote:
> The layers are necessary because the transistors are more densely
> packed than wires can be.  Wires don't scale like silicon.

Actually, it's a bit different. If you just shrink down a design, you'll see
that R remained constant (supposed the height of the wire didn't change), C
up and down is reduced as well, and C to the sides increases. Overall, you
can say the RC constant of the wire hasn't changed. So it doesn't scale
like the transistors, where the RC constant improves. That's why wire speed
dominates recent processes, and shrinks don't give much performance
improvements.

However, for the number of layers, there's a completely different
consideration, and that depends on how many gates you want to connect on a
chip, and how long the average connection is. With more gates, the average
wire length goes up. So you approximately need one additional metal layer
when you double the gate numbers on a chip.

This rule of thumb doesn't apply for tiled chips. There, each tile is a
separate entity, and since it only communicates with the neighbors, no
longer wires are needed. You can create your tile, route it as dense as
possible (e.g. with 6 metal layers), and then replicate it - you won't need
more layers, as this is not a hierarchical connection, but a flat one.

> Copper helped quite a bit, but there is nowhere to go from there.

There is: carbon nanotubes.

-- 
Bernd Paysan
"If you want it done right, you have to do it yourself"
http://www.jwdt.com/~paysan/

Guy Macon <http://www.guymacon.com/> wrote:

>Wes Newell wrote:
>>
>>It's a new cpu. Right now only supported with Linux. Which is fine with
>>me. I don't use Microsloth anyway.
>
>It seems strange to me that they say the following things:
>
>[1] It runs Linux.
>
>[2] It has a new instruction set and architecture
>
>[3] The C/C++ compiler is still in the future.
>
>What's wrong with this picture?

I don't know.  What?