Oscillator and Corruption of Registers

On Fri, 16 Nov 2007 20:05:18 GMT, in comp.arch.embedded Vladimir
Vassilevsky <antispam_bogus@hotmail.com> wrote:

>
>
>larwe wrote:
>
>> In a dynamic processor (ie. one that cannot live if its clock is
>> stopped), the registers are essentially DRAM cells.
>
>There were two typical architectures for that purpose: two phase and 
>four phase.
>
>The last dynamic CPU probably was the original i8080. Since then all 
>general purpose CPU designs were static.
>
>> If they don't get
>> refreshed, they decay. How much margin you have there to under-clock
>> the device depends on the individual chip production variations,
>> temperature, voltage, etc etc.
>
>The underclocking margin on the modern CPUs is governed by the 
>operational limits of the internal PLL.
>
>Vladimir Vassilevsky
>DSP and Mixed Signal Design Consultant
>http://www.abvolt.com

Montgomery Scott was suspended in a transporter buffer for over 75
years, due to a power failure,


Martin

On Fri, 16 Nov 2007 19:27:52 -0500, CBFalconer <cbfalconer@yahoo.com>
wrote:

>Vladimir Vassilevsky wrote:
>> larwe wrote:
>> 
>>> In a dynamic processor (ie. one that cannot live if its clock is
>>> stopped), the registers are essentially DRAM cells.
>> 
>> There were two typical architectures for that purpose: two phase and
>> four phase.
>> 
>> The last dynamic CPU probably was the original i8080. Since then all
>> general purpose CPU designs were static.
>
>IIRC the 8080 (and z80) was static. It could be halted without
>harm.

The Z80 and possibly 8085 could have been static, but at least the TI
variant of 8080 (TMS8080) specified 2 us maximum clock cycle time.
Also the 8080 clock driver (8224) had high CPU clock drive capability
(typically required by a dynamic construction). Also MC6800 needed
quite high two phase clock drive capability and the clock frequency
range was specified as 0.1-1 MHz, also suggesting a dynamic
construction.

One of the sales arguments for the CMOS RCA 1802 was that it was fully
static and the clock could be stopped or manually single stepped. This
would suggest that many competitors did not have this capability at
that time-

Paul
 

Paul Keinanen wrote:
> CBFalconer <cbfalconer@yahoo.com> wrote:
>> Vladimir Vassilevsky wrote:
>>> larwe wrote:
>>>
>>>> In a dynamic processor (ie. one that cannot live if its clock
>>>> is stopped), the registers are essentially DRAM cells.
>>>
>>> There were two typical architectures for that purpose: two phase
>>> and four phase.
>>>
>>> The last dynamic CPU probably was the original i8080. Since then
>>> all general purpose CPU designs were static.
>>
>> IIRC the 8080 (and z80) was static. It could be halted without
>> harm.
> 
> The Z80 and possibly 8085 could have been static, but at least the
> TI variant of 8080 (TMS8080) specified 2 us maximum clock cycle
> time. Also the 8080 clock driver (8224) had high CPU clock drive
> capability (typically required by a dynamic construction). Also
> MC6800 needed quite high two phase clock drive capability and the
> clock frequency range was specified as 0.1-1 MHz, also suggesting
> a dynamic construction.
> 
> One of the sales arguments for the CMOS RCA 1802 was that it was
> fully static and the clock could be stopped or manually single
> stepped. This would suggest that many competitors did not have
> this capability at that time-

It is not impossible that my memory is faulty.  I know I could halt
my systems at any point at any time.  However, it might have been
continuous application of the wait signal.

-- 
 Chuck F (cbfalconer at maineline dot net)
   <http://cbfalconer.home.att.net>
   Try the download section.



-- 
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"CBFalconer" <cbfalconer@yahoo.com> wrote in message
news:473E3588.A515BB61@yahoo.com...
> Vladimir Vassilevsky wrote:

> > The last dynamic CPU probably was the original i8080. Since then all
> > general purpose CPU designs were static.
>
> IIRC the 8080 (and z80) was static. It could be halted without
> harm.

You couldn't stop a CPU clock, at least for the original i8080. However
there used to be many remakes of i8080 which were full static. Some even
could run on the single +5V supply,  whereas the original 8080 required +/-5
and +12. AFAIK the original Z80 was static, however there was a limit for
the maximum duration of the clock in low. Power dissipation?

BTW my favourite ~25 year old RPN calculator is P-MOS dynamic 4-phase serial
architecture.

Vladimir Vassilevsky
DSP and Mixed Signal Consultant
www.abvolt.com