POP-11 (PDP-11/40 in an FPGA)

I am delighted in this interest in FPGA pdp-11s. I hope you folks have a
blast. I am going to build one from scratch some day when I have the time.

I wonder if there is slightly more verisimilitude in an FPGA
reimplementation if one goes to the effort of buliding a datapath adapted
from original processor schematics.
Anyway, thanks to the great directions of Jonathan Engdahl
http://home.alltel.net/engdahl/PDP-11_53.htm about five years ago I
converted a KDJ11 to a 'pdp-11/53', with an integrated 1.5 MB of RAM, clock,
serial, etc., put it in an old MicroVax QBUS chassis with a DEQNA (?)
network card and a CMD QBUS (T)MSCP SCSI controller and a few other things.
It runs 2.11 BSD.

I think I had better power it up again before I forget entirely how to do
so.

In my garage awaits a treasure, an actual pdp-11/45, a grotty looking RK05,
and a DecWriter. It is not the 11 that I learned Unix on (Waterloo Math UNIX
(modified v6) in 1979 in MC6098A) but is one of its sister machines, CCNG A
or D, from the Waterloo Electrical Engineering department's Computer
Communications Network Group, from Waterloo, to Bellevue, WA, by way of
South Carolina. It is pictured here, prior to arriving in my garage:
http://www.woffordwitch.com/PDP1145.asp. I cannot just plug it in and see
what happens. Rather I am going to have to learn about reconditioning old
power supplies and so forth. Someday!

Happy hacking,
Jan. Start a New Thread

--- In f..., "Austin Franklin"
wrote:
>
> Hi Richard,
>
> > The only 'gotcha' I can see is the fact that the Spartan
> > 3 FPGA is not 5V tolerant and the hard disk is 5V logic.
> > There are level shifters to deal with this.
>
> Spartan-3/-3E I/O can be made 5V-tolerant by using an external series
> current limiting resistor to limit the current into the upper clamp
diode to
> 10 mA. This makes the input 5V-tolerant. If the I/O is TTL, which it
> probably is, you can drive it with a CMOS output, and the swing will
be TTL
> compliant, which is a low below .8V and a high above 2V.
>
> Regards,
>
> Austin
>

I know this was the case for the Spartan IIE where a simple 100 ohm
resistor was sufficient to protect the inputs. However, Xilinx stated
that this resistor/tolerant solution would work on the IIE.

I haven't been able to find any Xilinx documentation suggesting that
the resistor solution would work on the Spartan 3.

I do see where Digilent used 270 ohm resistors on the Keyboard PS2
inputs because they do allow the keyboard to be driven with either 5V
or 3.3V from the S3 board. So, it must work!

I'll keep reading - it has to be there somewhere.

Richard Start a New Thread

On Wed, 2007-08-22 at 23:44 +0000, rtstofer wrote:
> An Altera board that seems more than adequate would be the Cyclone II
> FPGA Starter Development Kit. At $150 is is reasonable and has 8 MB
> of SDRAM as well as 32KB of SRAM and 4 MB Flash. It has a lot of
> gadgets (audio CODEC, 10 switches, 4 pushbuttons, 18 LEDs and 4 ea 7
> segment display) but the best part is that it has two 40 pin expansion
> ports with 36 signals each. With a little cable juxtaposition, one of
> these would drive an ATA drive quite nicely.

My favorite board, which I used to implement my 32-bit processor
on, is this one from XESS:
http://www.xess.com/prod039.php3
1M Spartan-3, 32 MByte SDRAM, 2 MByte Flash (holds FPGA bitstring
and resident ROM monitor for my system), keyboard port, VGA port,
parallel port, Ethernet, serial port, IDE interface, much more...

I'm in the process of porting UNIX 7th Edition to this system.
I choose V7 because it has a reasonably small code base. I would
have chosen V6, but the C syntax is (nowadays) non-standard and,
more important, the context switch mechanism is not portable,
as Dennis Ritchie explained:
http://www.cs.bell-labs.com/who/dmr/odd.html
This was corrected in V7.

Hellwig Start a New Thread

Austin wrote:
> Spartan-3/-3E I/O can be made 5V-tolerant by using an external series
> current limiting resistor to limit the current into the upper clamp diode
> to
> 10 mA. This makes the input 5V-tolerant. If the I/O is TTL, which it
> probably is,

If you're talking about the ATA disk, or a CF card, they are specified
at TTL input thresholds, but are usually implemented with CMOS logic,
so any outputs from the disk or card will swing close to the rail.
Series resistors might be adequate for old, slow ATA modes, but will
likely not work if you try to do the faster DMA modes.

Eric Start a New Thread

woodelf wrote:
> Unix does cheat however, most of the people back then time sharing
> tended only to use small sized programs rather than the monster sized
> programs of today.

Writing compact, efficient code is cheating?

> I/O I expect was often 300 baud too.

If you were using a DECwriter or the like. If you used a Teletype,
it was 110. If you used a glass TTY, it might have been 9600.

Eric Start a New Thread

Hi Hellwig, etal

I also have an XESS XSA-3S1000 and XST3.0 which I bought for another PDP
project. The XST 3.0 board has an IDE disk interface, but to the best of
my knowledge does not use series limit resisters. When I queried Dave
Vanden Bout from Xess about this, he said, and I quote:

"Most modern disks use 3.3V signals (actually LVTTL) on their IDE
interfaces, so there is no problem with the XSA board. You should
connect the IDE to CF adapters to use 3.3V."

I'm not sure what constitutes a "modern" disk drive, but it might be
worth testing the signals with a multimeter first. I was asking about
connecting Compact Flash which is why the CF reference. You must run CF
off a 3.3V rail, even though the CF to IDE adapters I bought have a
standard 3.5" floppy power connector on them.

If you want to interface an IDE drive to the Digilent Spartan 3 starter
board, a friend suggested using the Digilent Test Point Header 1 board
which has a male and female 2 x 20 pin connector which I believe allows
you to jumper the appropriate signals to the IDE pins.

An example is shown here:
http://www.mirrow.com/FPGApple/

Hi to Alex if you are on the list.

By the way ... thanks for the links Hellwig.

I found my way to St. Brian Kernigan's web site which was very
interesting. I must admit I expected something a little grander. But it
did have a few interesting tricks with PDP11 assembler code :-)

John.

Hellwig Geisse wrote:
>
> My favorite board, which I used to implement my 32-bit processor
> on, is this one from XESS:
> http://www.xess.com/prod039.php3
> 1M Spartan-3, 32 MByte SDRAM, 2 MByte Flash (holds FPGA bitstring
> and resident ROM monitor for my system), keyboard port, VGA port,
> parallel port, Ethernet, serial port, IDE interface, much more...
>
> I'm in the process of porting UNIX 7th Edition to this system.
> I choose V7 because it has a reasonably small code base. I would
> have chosen V6, but the C syntax is (nowadays) non-standard and,
> more important, the context switch mechanism is not portable,
> as Dennis Ritchie explained:
> http://www.cs.bell-labs.com/who/dmr/odd.html
>
> This was corrected in V7.
>
> Hellwig
>
>
>
>

--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent Start a New Thread

> When I queried Dave
> Vanden Bout from Xess about this, he said, and I quote:
>
> "Most modern disks use 3.3V signals (actually LVTTL) on their IDE
> interfaces, so there is no problem with the XSA board. You should
> connect the IDE to CF adapters to use 3.3V."

I have no idea what he said in that quote! There is more info at the
XESS site. The BurchEd IDE interface board for the Spartan IIE was
just a collection of resistors (100 ohms, I believe). It was
compatible with a HD or CF running on 5V (this is legal).

>
> If you want to interface an IDE drive to the Digilent Spartan 3 starter
> board, a friend suggested using the Digilent Test Point Header 1 board
> which has a male and female 2 x 20 pin connector which I believe allows
> you to jumper the appropriate signals to the IDE pins.

No such luck! The board has a male end connector and a female end
connector to allow it to be placed between the main board and other
gadgets plus a header in the middle. It is wired straight through.

I'm giving more consideration to the Altera board. It has 315 user
I/O which is more than the total pin count for the Spartan 3. Having
an extra 36 signal header makes it easy to connect a logic analyzer
while still having room for the CF/HDD.

I think I will use a CF device. It's not like this machine will get a
lot of use and I KNOW the CF device is 3.3V. OTOH, I wonder if the
swap partition will be overused (V6 does use swap, right?).

There is a draft of the 2008 ATA spec here:
http://t13.org/Documents/UploadedDocuments/project/d2008r7b-ATA-3.pdf
It appears that the output high voltage is at least 2.5V with a load
of 400 uA. It accepts an input high voltage of 2.0V. Given the
limited source current, I would think the resistors would work fine.
I might not choose to do it that way but I think it will work.

Richard Start a New Thread

On Thu, 2007-08-23 at 15:36 +0000, rtstofer wrote:

> I'm giving more consideration to the Altera board. It has 315 user
> I/O which is more than the total pin count for the Spartan 3. Having
> an extra 36 signal header makes it easy to connect a logic analyzer
> while still having room for the CF/HDD.

During the development of my CPU I had the problem that simulations
with Icarus Verilog and the actual implementation in the FPGA gave
different results. As I have no logic analyzer, I came up with the
following trick, which undoubtedly others have employed as well:
implement a bare-bones logic analyzer within the FPGA using block
RAM to catch the signals. When the buffer is full, read it out over
the serial line and display the results on a PC.

> I think I will use a CF device. It's not like this machine will get a
> lot of use and I KNOW the CF device is 3.3V. OTOH, I wonder if the
> swap partition will be overused (V6 does use swap, right?).

Yes, V6 does swapping.

Hellwig Start a New Thread

> During the development of my CPU I had the problem that simulations
> with Icarus Verilog and the actual implementation in the FPGA gave
> different results. As I have no logic analyzer, I came up with the
> following trick, which undoubtedly others have employed as well:
> implement a bare-bones logic analyzer within the FPGA using block
> RAM to catch the signals. When the buffer is full, read it out over
> the serial line and display the results on a PC.

Or, grab a spare Spartan 3 Starter Board and visit
http://www.sump.org/projects/analyzer/ I had a 200k gate version that
was undersized for my project but more than adequate for the logic
analyzer.

I like your idea of using BlockRAM. On my recent project, I didn't
have BlockRAM left over but for the POP11 I don't think BlockRAM will
be used at all. It might be cool to modify the sump.org project to
put the logic analyzer inside the FPGA permanently. There's plenty of
space. Maybe define a separate USART and connect an RS232 dongle.
Sample size will be limited by the size of BlockRAM or, on the Altera
board, use the 512KB of SRAM. That still leaves the 8 MB of SDRAM for
the POP-11 - although interfacing SDRAM to the POP-11 is much more
difficult than SRAM.

I REALLY like your idea!

Richard Start a New Thread

FWIW, the POP-11 code doesn't appear to handle a front panel. For a
first cut, that is probably ok but I really want the blinking lights
and switches. I might settle for 7 segment displays (in octal, of
course).

Anyone have a source for paddle handle toggle switches? Ok, now are
they reasonably priced?

Richard Start a New Thread