No problems.
Henk was rather good at milling front panels and so on, but not me.
JK.
b...@jetnet.ab.ca wrote:
>
> I think I want to get the hardware first designed, then worry about the
> display logic.
>
>
--
http://www.johnkent.com.au
http://members.optushome.com.au/jekent
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Small CPUs in FPGAs
Started by ●July 31, 2008
Reply by ●August 10, 20082008-08-10
Reply by ●August 10, 20082008-08-10
--- In f..., "Rick Collins" wrote:
>
> I am returning to my project to implement a small CPU in an FPGA. I
> had looked at some of Jan Gray's work back in 2002 or so. I don't see
> where he has done anything on those CPUs since then. The gr0040 looks
> to be very interesting, but it appears that he has not released the
> tools he developed.
What were you missing ?
IIRC, I found everything I needed in the zip file from J.Gray Webpage.
(I looked at it quite a while ago)
Cheers
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>
> I am returning to my project to implement a small CPU in an FPGA. I
> had looked at some of Jan Gray's work back in 2002 or so. I don't see
> where he has done anything on those CPUs since then. The gr0040 looks
> to be very interesting, but it appears that he has not released the
> tools he developed.
What were you missing ?
IIRC, I found everything I needed in the zip file from J.Gray Webpage.
(I looked at it quite a while ago)
Cheers
To post a message, send it to: f...
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Reply by ●August 10, 20082008-08-10
--- In f..., Hellwig Geisse
wrote:
> I developed my own 32 bit CPU "ECO32" together with a set of tools.
> However, I'm not sure if that counts as 'small'... :-)
>
> Briefly, the specs are:
> MIPS-like instruction set, but without floating-point
> hardware shift/multiply/divide unit
What are the major differences to e "real" MIPS I ?
> The hole project including all tools is open source and can
> be downloaded from
>
> http://homepages.fh-giessen.de/~hg53/eco32/
>
> (simulator, assembler/linker, FPGA implementation) and
>
> http://homepages.fh-giessen.de/~hg53/eos32/
Twice the same link ?
>
> (C compiler, many ROMs with test programs, machine monitor).
> the documentation is in a horrible state, I must confess...
;-)
Any plan to rewrite it to VHDL ?
(Amazed to find something written in Verilog on a german FH/UNI web
page ;-))
Cheers
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wrote:
> I developed my own 32 bit CPU "ECO32" together with a set of tools.
> However, I'm not sure if that counts as 'small'... :-)
>
> Briefly, the specs are:
> MIPS-like instruction set, but without floating-point
> hardware shift/multiply/divide unit
What are the major differences to e "real" MIPS I ?
> The hole project including all tools is open source and can
> be downloaded from
>
> http://homepages.fh-giessen.de/~hg53/eco32/
>
> (simulator, assembler/linker, FPGA implementation) and
>
> http://homepages.fh-giessen.de/~hg53/eos32/
Twice the same link ?
>
> (C compiler, many ROMs with test programs, machine monitor).
> the documentation is in a horrible state, I must confess...
;-)
Any plan to rewrite it to VHDL ?
(Amazed to find something written in Verilog on a german FH/UNI web
page ;-))
Cheers
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Reply by ●August 10, 20082008-08-10
--- In f..., "bfranchuk@..." wrote:
> Even with out front panels, here is some food for thought
> for a nice machine that is begging to be re-implimented again
> in hardware.
> [lilith ...]
I thought you have already boards with 2901/2903 in CPLDs ?
Cheers
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> Even with out front panels, here is some food for thought
> for a nice machine that is begging to be re-implimented again
> in hardware.
> [lilith ...]
I thought you have already boards with 2901/2903 in CPLDs ?
Cheers
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Reply by ●August 10, 20082008-08-10
On Sun, 2008-08-10 at 12:04 +0000, e2kcpu wrote:
> What are the major differences to e "real" MIPS I ?
Different instruction encoding, different special registers.
Generally an independent design, following the example in
Patterson/Hennessy. The instruction set is RISC-compatible
(in the sense that it can efficiently be run on a pipeline),
but my implementation isn't yet (it's a multicycle CPU,
but it is my intention to do a pipelined design next, as
soon as I have an operating system running on it).
> > http://homepages.fh-giessen.de/~hg53/eco32/
> > http://homepages.fh-giessen.de/~hg53/eos32/
>
> Twice the same link ?
No.
> Any plan to rewrite it to VHDL ?
> (Amazed to find something written in Verilog on a german FH/UNI web
> page ;-))
Well, I had to decide the language question when I started
teaching a course on "Hardware for Embedded Systems". I designed
a set of assignments and worked out solutions in both Verilog and
VHDL. IMO, the biggest difficulty for CS students is the fact that
these languages describe (parallel) hardware and not (sequential)
software. The difference in syntax then is a rather small matter.
Eventually I discovered this 12 year old contest:
http://www.cl.cam.ac.uk/~mjcg/Verilog/Cooley-VHDL-Verilog.html
and I decided in favour of Verilog... ;-)
Best regards,
Hellwig
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> What are the major differences to e "real" MIPS I ?
Different instruction encoding, different special registers.
Generally an independent design, following the example in
Patterson/Hennessy. The instruction set is RISC-compatible
(in the sense that it can efficiently be run on a pipeline),
but my implementation isn't yet (it's a multicycle CPU,
but it is my intention to do a pipelined design next, as
soon as I have an operating system running on it).
> > http://homepages.fh-giessen.de/~hg53/eco32/
> > http://homepages.fh-giessen.de/~hg53/eos32/
>
> Twice the same link ?
No.
> Any plan to rewrite it to VHDL ?
> (Amazed to find something written in Verilog on a german FH/UNI web
> page ;-))
Well, I had to decide the language question when I started
teaching a course on "Hardware for Embedded Systems". I designed
a set of assignments and worked out solutions in both Verilog and
VHDL. IMO, the biggest difficulty for CS students is the fact that
these languages describe (parallel) hardware and not (sequential)
software. The difference in syntax then is a rather small matter.
Eventually I discovered this 12 year old contest:
http://www.cl.cam.ac.uk/~mjcg/Verilog/Cooley-VHDL-Verilog.html
and I decided in favour of Verilog... ;-)
Best regards,
Hellwig
To post a message, send it to: f...
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Reply by ●August 10, 20082008-08-10
--- In f..., Hellwig Geisse
wrote:
>
> On Sun, 2008-08-10 at 12:04 +0000, e2kcpu wrote:
>
> > What are the major differences to e "real" MIPS I ?
>
> Different instruction encoding, different special registers.
> Generally an independent design, following the example in
> Patterson/Hennessy. The instruction set is RISC-compatible
> (in the sense that it can efficiently be run on a pipeline),
> but my implementation isn't yet (it's a multicycle CPU,
> but it is my intention to do a pipelined design next, as
> soon as I have an operating system running on it).
OK. You only ported LCC to it ?
I didn't see any GNU Tools there ...
Ever took a look at PCC ? Produces much better code ...
> > > http://homepages.fh-giessen.de/~hg53/eco32/
> > > http://homepages.fh-giessen.de/~hg53/eos32/
> >
> > Twice the same link ?
>
> No.
Sorry, that's what I get for replying to email before coffee ;-)
> > Any plan to rewrite it to VHDL ?
> Eventually I discovered this 12 year old contest:
>
> http://www.cl.cam.ac.uk/~mjcg/Verilog/Cooley-VHDL-Verilog.html
>
> and I decided in favour of Verilog... ;-)
VERY fun reading for a Sunday morning,
thanks !
Cheers
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wrote:
>
> On Sun, 2008-08-10 at 12:04 +0000, e2kcpu wrote:
>
> > What are the major differences to e "real" MIPS I ?
>
> Different instruction encoding, different special registers.
> Generally an independent design, following the example in
> Patterson/Hennessy. The instruction set is RISC-compatible
> (in the sense that it can efficiently be run on a pipeline),
> but my implementation isn't yet (it's a multicycle CPU,
> but it is my intention to do a pipelined design next, as
> soon as I have an operating system running on it).
OK. You only ported LCC to it ?
I didn't see any GNU Tools there ...
Ever took a look at PCC ? Produces much better code ...
> > > http://homepages.fh-giessen.de/~hg53/eco32/
> > > http://homepages.fh-giessen.de/~hg53/eos32/
> >
> > Twice the same link ?
>
> No.
Sorry, that's what I get for replying to email before coffee ;-)
> > Any plan to rewrite it to VHDL ?
> Eventually I discovered this 12 year old contest:
>
> http://www.cl.cam.ac.uk/~mjcg/Verilog/Cooley-VHDL-Verilog.html
>
> and I decided in favour of Verilog... ;-)
VERY fun reading for a Sunday morning,
thanks !
Cheers
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Reply by ●August 10, 20082008-08-10
On Sun, 2008-08-10 at 14:04 +0000, e2kcpu wrote:
> OK. You only ported LCC to it ?
Yes. This was in fact very easy.
> Ever took a look at PCC ? Produces much better code ...
No, I didn't. I'm surprised to see that it now understands
ANSI-C. Very interesting, thanks.
Hellwig
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> OK. You only ported LCC to it ?
Yes. This was in fact very easy.
> Ever took a look at PCC ? Produces much better code ...
No, I didn't. I'm surprised to see that it now understands
ANSI-C. Very interesting, thanks.
Hellwig
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Reply by ●August 10, 20082008-08-10
--- In f..., "e2kcpu" wrote:
>
> --- In f..., "Rick Collins" wrote:
> >
> > I am returning to my project to implement a small CPU in an FPGA. I
> > had looked at some of Jan Gray's work back in 2002 or so. I don't see
> > where he has done anything on those CPUs since then. The gr0040 looks
> > to be very interesting, but it appears that he has not released the
> > tools he developed.
>
> What were you missing ?
> IIRC, I found everything I needed in the zip file from J.Gray Webpage.
> (I looked at it quite a while ago)
Perhaps you are thinking of the xr16? That was completely published
and an LCC port was provided. The gr0040 was not fully documented and
the web site even says the compiler was ported, but not provided.
The significance of the gr0040 and related designs seems to be the low
LUT count. But I believe this was using TBUFs for multiplexers and
they are no longer used in FPGAs. Now you have to use LUTs to created
muxes and it can be rather expensive. When I created my ALU,
recognizing this, I used the adder/logic unit to mux the TOS and NOS
into the TOS input mux. This saved one block of LUTs. Still, at
around 100 LUTs that input mux was the largest structure in the entire
CPU. Otherwise the design was pretty small.
Rick
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>
> --- In f..., "Rick Collins" wrote:
> >
> > I am returning to my project to implement a small CPU in an FPGA. I
> > had looked at some of Jan Gray's work back in 2002 or so. I don't see
> > where he has done anything on those CPUs since then. The gr0040 looks
> > to be very interesting, but it appears that he has not released the
> > tools he developed.
>
> What were you missing ?
> IIRC, I found everything I needed in the zip file from J.Gray Webpage.
> (I looked at it quite a while ago)
Perhaps you are thinking of the xr16? That was completely published
and an LCC port was provided. The gr0040 was not fully documented and
the web site even says the compiler was ported, but not provided.
The significance of the gr0040 and related designs seems to be the low
LUT count. But I believe this was using TBUFs for multiplexers and
they are no longer used in FPGAs. Now you have to use LUTs to created
muxes and it can be rather expensive. When I created my ALU,
recognizing this, I used the adder/logic unit to mux the TOS and NOS
into the TOS input mux. This saved one block of LUTs. Still, at
around 100 LUTs that input mux was the largest structure in the entire
CPU. Otherwise the design was pretty small.
Rick
To post a message, send it to: f...
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Reply by ●August 10, 20082008-08-10
--- In f..., "Rick Collins" wrote:
>
> --- In f..., "e2kcpu" wrote:
> > What were you missing ?
> > IIRC, I found everything I needed in the zip file from J.Gray Webpage.
> > (I looked at it quite a while ago)
>
> Perhaps you are thinking of the xr16? That was completely published
> and an LCC port was provided. The gr0040 was not fully documented and
> the web site even says the compiler was ported, but not provided.
Yup, I just checked, and you are right. I mixed it up, sorry.
But the gr0040 is still available, and just run it through P&R ...
> The significance of the gr0040 and related designs seems to be the low
> LUT count. But I believe this was using TBUFs for multiplexers and
> they are no longer used in FPGAs. Now you have to use LUTs to created
> muxes and it can be rather expensive. When I created my ALU,
> recognizing this, I used the adder/logic unit to mux the TOS and NOS
> into the TOS input mux. This saved one block of LUTs. Still, at
> around 100 LUTs that input mux was the largest structure in the entire
> CPU. Otherwise the design was pretty small.
But that's something we have to deal now with, as all the newer FPGAs
are having the same structure :(
Cheers
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>
> --- In f..., "e2kcpu" wrote:
> > What were you missing ?
> > IIRC, I found everything I needed in the zip file from J.Gray Webpage.
> > (I looked at it quite a while ago)
>
> Perhaps you are thinking of the xr16? That was completely published
> and an LCC port was provided. The gr0040 was not fully documented and
> the web site even says the compiler was ported, but not provided.
Yup, I just checked, and you are right. I mixed it up, sorry.
But the gr0040 is still available, and just run it through P&R ...
> The significance of the gr0040 and related designs seems to be the low
> LUT count. But I believe this was using TBUFs for multiplexers and
> they are no longer used in FPGAs. Now you have to use LUTs to created
> muxes and it can be rather expensive. When I created my ALU,
> recognizing this, I used the adder/logic unit to mux the TOS and NOS
> into the TOS input mux. This saved one block of LUTs. Still, at
> around 100 LUTs that input mux was the largest structure in the entire
> CPU. Otherwise the design was pretty small.
But that's something we have to deal now with, as all the newer FPGAs
are having the same structure :(
Cheers
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Reply by ●August 10, 20082008-08-10
John Kent wrote:
> An alternative to using a keypad for the toggle switches would also be
> to use a mouse to toggle the switches on the VGA display.
>
> I note the FP6120. The problem with the Intersil (?) 6120 chip was that
> my friends wanted to emulate the Digital buses for the PDP-8 (Posibus
> and so on) so they could interface old hardware and the 6120 did not
> generate the correct bus signals. I have not heard from the guys in
> quite a while, so I'm not sure what they did in the end. I was
> originally approached by Henk Gooijens, who runs the www.pdp-11.nl web
> site who wanted a faster 6809 to run his PDP-8 emulator on. The emulator
> was actually originally written by a good friend, Frank Wilson, who I
> know from the Flex User Group mailing list. I suggested Henk could
> emulate the entire PDP-8 processor in an FPGA, and Hans Pufal was kind
> enough to offer us his PDP-8 design.
>
>
Well I like CPLD's rather than FPGA's since you don't need a boot
prom for the CPLD's. The maintance manuals for the PDP's are on-line
http://bitsavers.trailing-edge.com/ I suspect that is where to start
as well as looking at Simh for emulation as the hardware for the old
machines had a lot of gota ya's design features based on qurks of the
hardware used. A simple PDP8 with 4K of memory is easy ...
A full featured one with hardware floating point, 32K of memory
and timeshareing hardware is very tricky make right.
> John.
>
>
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> An alternative to using a keypad for the toggle switches would also be
> to use a mouse to toggle the switches on the VGA display.
>
> I note the FP6120. The problem with the Intersil (?) 6120 chip was that
> my friends wanted to emulate the Digital buses for the PDP-8 (Posibus
> and so on) so they could interface old hardware and the 6120 did not
> generate the correct bus signals. I have not heard from the guys in
> quite a while, so I'm not sure what they did in the end. I was
> originally approached by Henk Gooijens, who runs the www.pdp-11.nl web
> site who wanted a faster 6809 to run his PDP-8 emulator on. The emulator
> was actually originally written by a good friend, Frank Wilson, who I
> know from the Flex User Group mailing list. I suggested Henk could
> emulate the entire PDP-8 processor in an FPGA, and Hans Pufal was kind
> enough to offer us his PDP-8 design.
>
>
Well I like CPLD's rather than FPGA's since you don't need a boot
prom for the CPLD's. The maintance manuals for the PDP's are on-line
http://bitsavers.trailing-edge.com/ I suspect that is where to start
as well as looking at Simh for emulation as the hardware for the old
machines had a lot of gota ya's design features based on qurks of the
hardware used. A simple PDP8 with 4K of memory is easy ...
A full featured one with hardware floating point, 32K of memory
and timeshareing hardware is very tricky make right.
> John.
>
>
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