Hi, I need to fix the reset problem on some older
LPC2124, and need a very low freq crystal oscillator.
Did anybody try running the PLL with Crystal/Osc Fosc
around 3.68Mhz?? Is PLL stable at that range??
The datasheet and application note say PLL only
working in the 10-25MHz Fosc range.
(Note: I can get around with the 10Mhz-25Mhz fosc
requirement for ISP. Only checking if PLL is stable)
Regards
LPC2124's PLL working with 3.68Mhz fosc??
Started by ●October 19, 2006
Reply by ●October 19, 20062006-10-19
--- In l..., "unity0724" wrote:
>
> Hi, I need to fix the reset problem on some older
> LPC2124, and need a very low freq crystal oscillator.
>
> Did anybody try running the PLL with Crystal/Osc Fosc
> around 3.68Mhz?? Is PLL stable at that range??
>
> The datasheet and application note say PLL only
> working in the 10-25MHz Fosc range.
>
> (Note: I can get around with the 10Mhz-25Mhz fosc
> requirement for ISP. Only checking if PLL is stable)
>
> Regards
The PLL supports 1-50MHz. End user specifications has been limited
(to 10-25MHz) becuase the boot loader cannot cope with such a wide range.
Jaya
>
> Hi, I need to fix the reset problem on some older
> LPC2124, and need a very low freq crystal oscillator.
>
> Did anybody try running the PLL with Crystal/Osc Fosc
> around 3.68Mhz?? Is PLL stable at that range??
>
> The datasheet and application note say PLL only
> working in the 10-25MHz Fosc range.
>
> (Note: I can get around with the 10Mhz-25Mhz fosc
> requirement for ISP. Only checking if PLL is stable)
>
> Regards
The PLL supports 1-50MHz. End user specifications has been limited
(to 10-25MHz) becuase the boot loader cannot cope with such a wide range.
Jaya
Reply by ●October 19, 20062006-10-19
--- In l..., "jayasooriah"
wrote:
>
> --- In l..., "unity0724" wrote:
> >
> > Hi, I need to fix the reset problem on some older
> > LPC2124, and need a very low freq crystal oscillator.
> >
> > Did anybody try running the PLL with Crystal/Osc Fosc
> > around 3.68Mhz?? Is PLL stable at that range??
> >
> > The datasheet and application note say PLL only
> > working in the 10-25MHz Fosc range.
> >
> > (Note: I can get around with the 10Mhz-25Mhz fosc
> > requirement for ISP. Only checking if PLL is stable)
> >
> > Regards
>
> The PLL supports 1-50MHz. End user specifications has been limited
> (to 10-25MHz) becuase the boot loader cannot cope with such a wide
> range.
>
> Jaya
>
Hello!
I'm only interested in:
- Getting that LPC2124 reset problem fixed! (or minimized)
- Checking if LPC2124 PLL is stable with 3.68MHz fosc
I Do NOT have any interest in the bootloader issue...
unless your bootloader is able to fix the LPC2124 reset
problem... :)
And, Sorry, where is that "The PLL supports 1-50MHz" from?
I cannot find it from user manual.
Could only find: "The PLL accepts an input clock frequency
in the range of 10 MHz to 25 MHz only" from user manual.
You happen to have another customer running the PLL below
10Mhz??
Regards
wrote:
>
> --- In l..., "unity0724" wrote:
> >
> > Hi, I need to fix the reset problem on some older
> > LPC2124, and need a very low freq crystal oscillator.
> >
> > Did anybody try running the PLL with Crystal/Osc Fosc
> > around 3.68Mhz?? Is PLL stable at that range??
> >
> > The datasheet and application note say PLL only
> > working in the 10-25MHz Fosc range.
> >
> > (Note: I can get around with the 10Mhz-25Mhz fosc
> > requirement for ISP. Only checking if PLL is stable)
> >
> > Regards
>
> The PLL supports 1-50MHz. End user specifications has been limited
> (to 10-25MHz) becuase the boot loader cannot cope with such a wide
> range.
>
> Jaya
>
Hello!
I'm only interested in:
- Getting that LPC2124 reset problem fixed! (or minimized)
- Checking if LPC2124 PLL is stable with 3.68MHz fosc
I Do NOT have any interest in the bootloader issue...
unless your bootloader is able to fix the LPC2124 reset
problem... :)
And, Sorry, where is that "The PLL supports 1-50MHz" from?
I cannot find it from user manual.
Could only find: "The PLL accepts an input clock frequency
in the range of 10 MHz to 25 MHz only" from user manual.
You happen to have another customer running the PLL below
10Mhz??
Regards
Reply by ●October 19, 20062006-10-19
--- In l..., "unity0724" wrote:
> Hello!
> I'm only interested in:
> - Getting that LPC2124 reset problem fixed! (or minimized)
> - Checking if LPC2124 PLL is stable with 3.68MHz fosc
>
> I Do NOT have any interest in the bootloader issue...
> unless your bootloader is able to fix the LPC2124 reset
> problem... :)
>
> And, Sorry, where is that "The PLL supports 1-50MHz" from?
> I cannot find it from user manual.
> Could only find: "The PLL accepts an input clock frequency
> in the range of 10 MHz to 25 MHz only" from user manual.
>
> You happen to have another customer running the PLL below
> 10Mhz??
>
> Regards
I don't know what your reset problem is. I was only responding to
your question alluded to by the title "PLL working with 3.68Mhz fosc".
I know that the PLL used in the LPC family is specified as 1-50 MHz.
Therefore it will work at 3.68 MHz. I have seen it in working outside
the 10-25 MHz range.
I am told that it was limited to 10-25 MHz in the user manual because
of boot loader support issues. I do not know what the issues are.
I can say however that I have not had any problems with my boot loader
with the full 1-50 MHz range.
Good luck.
Jaya
> Hello!
> I'm only interested in:
> - Getting that LPC2124 reset problem fixed! (or minimized)
> - Checking if LPC2124 PLL is stable with 3.68MHz fosc
>
> I Do NOT have any interest in the bootloader issue...
> unless your bootloader is able to fix the LPC2124 reset
> problem... :)
>
> And, Sorry, where is that "The PLL supports 1-50MHz" from?
> I cannot find it from user manual.
> Could only find: "The PLL accepts an input clock frequency
> in the range of 10 MHz to 25 MHz only" from user manual.
>
> You happen to have another customer running the PLL below
> 10Mhz??
>
> Regards
I don't know what your reset problem is. I was only responding to
your question alluded to by the title "PLL working with 3.68Mhz fosc".
I know that the PLL used in the LPC family is specified as 1-50 MHz.
Therefore it will work at 3.68 MHz. I have seen it in working outside
the 10-25 MHz range.
I am told that it was limited to 10-25 MHz in the user manual because
of boot loader support issues. I do not know what the issues are.
I can say however that I have not had any problems with my boot loader
with the full 1-50 MHz range.
Good luck.
Jaya
Reply by ●October 19, 20062006-10-19
--- In l..., "jayasooriah"
wrote:
>
> --- In l..., "unity0724" wrote:
>
> > Hello!
> > I'm only interested in:
> > - Getting that LPC2124 reset problem fixed! (or minimized)
> > - Checking if LPC2124 PLL is stable with 3.68MHz fosc
> >
> > I Do NOT have any interest in the bootloader issue...
> > unless your bootloader is able to fix the LPC2124 reset
> > problem... :)
> >
> > And, Sorry, where is that "The PLL supports 1-50MHz" from?
> > I cannot find it from user manual.
> > Could only find: "The PLL accepts an input clock frequency
> > in the range of 10 MHz to 25 MHz only" from user manual.
> >
> > You happen to have another customer running the PLL below
> > 10Mhz??
> >
> > Regards
>
> I don't know what your reset problem is. I was only responding to
> your question alluded to by the title "PLL working with 3.68Mhz
fosc".
>
> I know that the PLL used in the LPC family is specified as 1-50
MHz.
> Therefore it will work at 3.68 MHz. I have seen it in working
outside
> the 10-25 MHz range.
>
> I am told that it was limited to 10-25 MHz in the user manual
because
> of boot loader support issues. I do not know what the issues are.
>
> I can say however that I have not had any problems with my boot
loader
> with the full 1-50 MHz range.
>
> Good luck.
>
> Jaya
>
Ooops,
I happen to know that the PLL is specified from 10-25 MHz input
only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
needed to make an external crystal run can support 1-50 MHz, not the
PLL.
We did test the PLL below 10 MHz and it locked reliably at least
down to 5 MHz. There were no thorough tests done below 5 MHz as this
is already way out of spec. What we could see, the jitter increased
a lot when using the PLL with 5 MHz input.
To get the reset problem fixed on the 2124, you actually need to
follow the instructions in the Errata Sheet, a double reset with the
given minimum time in between will fix it.
There is also a version LPC2124/00 which has the startup problem
fixed in hardware.
It is however correct that a lower external input frequency reduces
the likelyhood of the startup problem to occur.
nxp_apps
wrote:
>
> --- In l..., "unity0724" wrote:
>
> > Hello!
> > I'm only interested in:
> > - Getting that LPC2124 reset problem fixed! (or minimized)
> > - Checking if LPC2124 PLL is stable with 3.68MHz fosc
> >
> > I Do NOT have any interest in the bootloader issue...
> > unless your bootloader is able to fix the LPC2124 reset
> > problem... :)
> >
> > And, Sorry, where is that "The PLL supports 1-50MHz" from?
> > I cannot find it from user manual.
> > Could only find: "The PLL accepts an input clock frequency
> > in the range of 10 MHz to 25 MHz only" from user manual.
> >
> > You happen to have another customer running the PLL below
> > 10Mhz??
> >
> > Regards
>
> I don't know what your reset problem is. I was only responding to
> your question alluded to by the title "PLL working with 3.68Mhz
fosc".
>
> I know that the PLL used in the LPC family is specified as 1-50
MHz.
> Therefore it will work at 3.68 MHz. I have seen it in working
outside
> the 10-25 MHz range.
>
> I am told that it was limited to 10-25 MHz in the user manual
because
> of boot loader support issues. I do not know what the issues are.
>
> I can say however that I have not had any problems with my boot
loader
> with the full 1-50 MHz range.
>
> Good luck.
>
> Jaya
>
Ooops,
I happen to know that the PLL is specified from 10-25 MHz input
only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
needed to make an external crystal run can support 1-50 MHz, not the
PLL.
We did test the PLL below 10 MHz and it locked reliably at least
down to 5 MHz. There were no thorough tests done below 5 MHz as this
is already way out of spec. What we could see, the jitter increased
a lot when using the PLL with 5 MHz input.
To get the reset problem fixed on the 2124, you actually need to
follow the instructions in the Errata Sheet, a double reset with the
given minimum time in between will fix it.
There is also a version LPC2124/00 which has the startup problem
fixed in hardware.
It is however correct that a lower external input frequency reduces
the likelyhood of the startup problem to occur.
nxp_apps
Reply by ●October 19, 20062006-10-19
---- Original Message ----
From: "nxp_apps"
To:
Sent: Thursday, October 19, 2006 5:04 PM
Subject: [lpc2000] Re: LPC2124's PLL working with 3.68Mhz fosc??
> To get the reset problem fixed on the 2124, you actually need to
> follow the instructions in the Errata Sheet, a double reset with the
> given minimum time in between will fix it.
>
> There is also a version LPC2124/00 which has the startup problem
> fixed in hardware.
What is the story with these /00 chips (LPC2114,2119,2124,2129)? They are
only mentioned in the errata sheets, and it is hinted that they are not the
same as the "B" revision. Do they fix more bugs than "B", or even add
features like fast GPIO?
Karl Olsen
From: "nxp_apps"
To:
Sent: Thursday, October 19, 2006 5:04 PM
Subject: [lpc2000] Re: LPC2124's PLL working with 3.68Mhz fosc??
> To get the reset problem fixed on the 2124, you actually need to
> follow the instructions in the Errata Sheet, a double reset with the
> given minimum time in between will fix it.
>
> There is also a version LPC2124/00 which has the startup problem
> fixed in hardware.
What is the story with these /00 chips (LPC2114,2119,2124,2129)? They are
only mentioned in the errata sheets, and it is hinted that they are not the
same as the "B" revision. Do they fix more bugs than "B", or even add
features like fast GPIO?
Karl Olsen
Reply by ●October 19, 20062006-10-19
> What is the story with these /00 chips
(LPC2114,2119,2124,2129)?
They are
> only mentioned in the errata sheets, and it is hinted that they are
not the
> same as the "B" revision. Do they fix more bugs than "B", or even
add
> features like fast GPIO?
>
> Karl Olsen
>
Karl,
the /00s have only one fix, that is the startup, nothing else fixed.
We are working on /01 versions that have all the fixes and will
include new features like the fast I/Os
Hope the /01s will be out in 1st quarter 07
nxp_apps
They are
> only mentioned in the errata sheets, and it is hinted that they are
not the
> same as the "B" revision. Do they fix more bugs than "B", or even
add
> features like fast GPIO?
>
> Karl Olsen
>
Karl,
the /00s have only one fix, that is the startup, nothing else fixed.
We are working on /01 versions that have all the fixes and will
include new features like the fast I/Os
Hope the /01s will be out in 1st quarter 07
nxp_apps
Reply by ●October 19, 20062006-10-19
--- In l..., "nxp_apps" wrote:
> I happen to know that the PLL is specified from 10-25 MHz input
> only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
> needed to make an external crystal run can support 1-50 MHz, not the
> PLL.
You may be right that the 1-50 MHz was only for the crystal
oscillator. We ran devices at 1 MHz (for purposes I rather not
discuss) and while we were not looking specifically for PLL jitter,
the indications are that there were no problems with PLL capture or
sustained operation.
Jaya
> I happen to know that the PLL is specified from 10-25 MHz input
> only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
> needed to make an external crystal run can support 1-50 MHz, not the
> PLL.
You may be right that the 1-50 MHz was only for the crystal
oscillator. We ran devices at 1 MHz (for purposes I rather not
discuss) and while we were not looking specifically for PLL jitter,
the indications are that there were no problems with PLL capture or
sustained operation.
Jaya
Reply by ●October 20, 20062006-10-20
--- In l..., "jayasooriah" wrote:
>
> --- In l..., "nxp_apps" wrote:
>
> > I happen to know that the PLL is specified from 10-25 MHz input
> > only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
> > needed to make an external crystal run can support 1-50 MHz, not the
> > PLL.
>
> You may be right that the 1-50 MHz was only for the crystal
> oscillator. We ran devices at 1 MHz (for purposes I rather not
> discuss) and while we were not looking specifically for PLL jitter,
> the indications are that there were no problems with PLL capture or
> sustained operation.
>
> Jaya
>
Jaya,
that is an interesting data point. Would not have thought this works.
Thanks for this input.
Bob
>
> --- In l..., "nxp_apps" wrote:
>
> > I happen to know that the PLL is specified from 10-25 MHz input
> > only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
> > needed to make an external crystal run can support 1-50 MHz, not the
> > PLL.
>
> You may be right that the 1-50 MHz was only for the crystal
> oscillator. We ran devices at 1 MHz (for purposes I rather not
> discuss) and while we were not looking specifically for PLL jitter,
> the indications are that there were no problems with PLL capture or
> sustained operation.
>
> Jaya
>
Jaya,
that is an interesting data point. Would not have thought this works.
Thanks for this input.
Bob
Reply by ●October 20, 20062006-10-20
Hi Jaya,
And if you were looking specifically for PLL jitter, where would you
look at?
When you say "sustained operation", do you mean over the entire
(specified) temp. range?
I am curious.
Best regards
Roger
--- In l..., "jayasooriah" wrote:
>
> --- In l..., "nxp_apps" wrote:
>
> > I happen to know that the PLL is specified from 10-25 MHz input
> > only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
> > needed to make an external crystal run can support 1-50 MHz, not the
> > PLL.
>
> You may be right that the 1-50 MHz was only for the crystal
> oscillator. We ran devices at 1 MHz (for purposes I rather not
> discuss) and while we were not looking specifically for PLL jitter,
> the indications are that there were no problems with PLL capture or
> sustained operation.
>
> Jaya
>
And if you were looking specifically for PLL jitter, where would you
look at?
When you say "sustained operation", do you mean over the entire
(specified) temp. range?
I am curious.
Best regards
Roger
--- In l..., "jayasooriah" wrote:
>
> --- In l..., "nxp_apps" wrote:
>
> > I happen to know that the PLL is specified from 10-25 MHz input
> > only, not from 1-50 MHz! The on-chip ciruit (basically an inverter)
> > needed to make an external crystal run can support 1-50 MHz, not the
> > PLL.
>
> You may be right that the 1-50 MHz was only for the crystal
> oscillator. We ran devices at 1 MHz (for purposes I rather not
> discuss) and while we were not looking specifically for PLL jitter,
> the indications are that there were no problems with PLL capture or
> sustained operation.
>
> Jaya
>
