Cortex-M Exception Handling (Part 2)
Exception entry and return on Cortex-M look simple, but the hardware does a lot to preserve context, enforce privilege, and pick the right stack. This post walks through the processor actions after an exception is accepted: which registers get pushed, how CONTROL, MSP and PSP affect stack selection, how EXC_RETURN encodes the return path, and why VTOR and vector table alignment matter for handler lookup.
Cortex-M Exception Handling (Part 1)
This article describes how Cortex-M processors handle interrupts and, more generally, exceptions, a concept that plays a central role in the design and implementation of most embedded systems.
Cortex-M Exception Handling (Part 2)
Exception entry and return on Cortex-M look simple, but the hardware does a lot to preserve context, enforce privilege, and pick the right stack. This post walks through the processor actions after an exception is accepted: which registers get pushed, how CONTROL, MSP and PSP affect stack selection, how EXC_RETURN encodes the return path, and why VTOR and vector table alignment matter for handler lookup.
Cortex-M Exception Handling (Part 1)
This article describes how Cortex-M processors handle interrupts and, more generally, exceptions, a concept that plays a central role in the design and implementation of most embedded systems.
Cortex-M Exception Handling (Part 1)
This article describes how Cortex-M processors handle interrupts and, more generally, exceptions, a concept that plays a central role in the design and implementation of most embedded systems.
Cortex-M Exception Handling (Part 2)
Exception entry and return on Cortex-M look simple, but the hardware does a lot to preserve context, enforce privilege, and pick the right stack. This post walks through the processor actions after an exception is accepted: which registers get pushed, how CONTROL, MSP and PSP affect stack selection, how EXC_RETURN encodes the return path, and why VTOR and vector table alignment matter for handler lookup.
