hey, I'll give a little background before I start, I've recently started with FPGA (I'm more used to PIC MCUs), which I'm planning to use with a high speed analog digital converter (all the MCUs I know are too slow to be used hence the FPGA), I "studied/learned" with free range VHDL, which I've finished. I'm using a lattice MachXO3L FPGA – LCMXO3L-6900C-5BG256C, but can switch to a Spartan 6.

I want an ADC to take samples from a pulse, and with these n samples fit a curve (like Gaussian or something similar). What I plan on getting te signals from the ADC derive them to get a cycle and then fit a curve, but I'm not sure how to fit a curve. Can someone point me in the right direction on how to do curve fitting on FPGAs? Or offer any suggestion or criticism?

thanks

Sounds like you have two problems:

1) Doing x

2) Implementing x on an FPGA

In your case x = 'curve fitting'

Figure out problem 1) in a high-level environment like Matlab/Octave or Python. Learn how to do it without using any libraries. There are a lot of different ways of doing curve fitting, with different trade-offs. When you feel you really fundamentaly understand how it works, then move to step 2

In step 2 you "simply" implement your understanding of step 1 in HDL. Usually I find I then discover I don't understand everything I need to about step 1, or I picked an inappropriate method (esp. in the early days before you have done much FPGA work) and have to iterate, getting more understanding.

This can be applied to any of the many 'how do I implement x on an FPGA' problems.

(Depending on *why* you want to do this, see also here: http://parallelpoints.com/why-use-an-fpga/)

do you recommend and book, site or anything on curve fitting? thanks for the site, it is something to think about.

Last time I did curve fitting, was a looong time ago, and I needed something which was 'incremental' rather than operating on all the data at once.

I used my textbook from university to create a parameter estimator:

Self-Tuning Systems: Control and Signal Processing P. E. Wellstead, M. B. Zarrop - http://eu.wiley.com/WileyCDA/WileyTitle/productCd-...

(Prof. Wellstead was my tutor too :)

Do you have a budget for this task ?

How fast must the ADC be (ie how many samples per second.)

Are you able to express the signal processing function in C or MATLAB.

If budget is big and task is important - pay someone to do it right or buy correct tools and expect to spend a lot of time on it.

Xilinx Vivado includes tools that can work in C or block diagrams but there is quite a learning curve.

Anything you can express in C can be expressed in VHDL but it might be hard work.

Lattice's tools are very basic.

If you need up market tools consider Xilinx Artix or Spartan 7, you can prototype on an ARTY board for $99 and use the free tools.

You don't really tell us enough to offer any definitive advice.

MK

hey,

dlypka: thaks, I'm looking into synflow.

: Yes you read correctly that's basically what I want to do.

I tried looking into buying a DSP, but I know no one who uses one, or that has used one

-the adc has a sample rate of 65 MSPS.

- I've noticed that lattice's tools are simple, compared to Altera's.

- the tools that I have available are the lattice, Spartan 6 and I can borrow a cyclone 3

You'll never get this to work without custom boards (ready made or your own) and good test gear unless you are either very, very experienced or very lucky.

MK

the adc is already on a board, I'm getting the data via a parallel port. I just need to read 12 pins which are referenced to ground. for clarification: Are the FPGAs that I have available unable to read at this rate?

This may sound a bit rude but you are not going about asking this in a sensible way.

If you already have some parts then tell us exactly what they are - which ADC type on which board connected how to an FPGA (so what type of Spartan 6 and on what kind of board.)

You need to read 12 pins from the ADC - well what are their functions ?

And so on.

MK

no problem, I don't find it rude at all, I have a Spartan-6 XC6SLX16-CSG324-2C FPGA, a lattice LCMXO3L-6900C and an ADC that gives me a 12 bit code FFF - 000. My problem comes in fitting a curve.

Sorry, I can't help you because you either can't or won't provide the level of information needed. So far you've told us that you have an unknown 12 bit ADC and two FPGA chips on unknown boards. That is not enough information, or even close to enough information.

It's like going to the doctor and saying you've got a pain, but then expecting them to guess where the pain is and what is wrong with you.

MK

To be honest, you'd be better off with DSP rather than FPGA.

Look at the Cx language on www.synflow.com.

Cx will enable you more likely to be able to port existing Curve-Fitting code from C or C++ into the FGPA.

Hello Kiyoshi,

If I read it correctly, you need some way for the FPGA to compute the functions that would typically be implemented in C or Python to derive the parameters of a known curve.

For example if you need to perform a linear regression (y = ax + b) on the sampled points, then you wish for the FPGA to compute the a and b values that minimise the least squared error or some other equivalent metric.

Why not look at some of the linear regression approaches that have been explored before and see if they serve as a basic proof of concept for what you are trying to do. In my opinion, there is also the ADC interfacing and display or output of the curve parameters that form a major chunk of the project in addition to the actual curve fitting algorithm

Why not just use higher sampling rate?

If you need to do curve fitting I suggest a DSP for this purpose since the level of mathematical computations required by the curve fitting (of course that depends on the chosen algorithm) is high. If you are determined to use a FPGA, perform the math on a soft-core cpu.

What might be really interesting here is that after you successfully coded the fitting algorithm on the soft core, you may speed it up, significantly, by designing hardware accelerators to do the bottle-nick tasks.