I am working with high speed ADC (200/250MSPS) to sample the signals and connect it to stm32f429 microcontroller.
How is it possible to handle such high speed ADC's as it cannot be directly connected to stm32? Can I use DSP or FPGA in between? How should it be done?
FPGA to run the ADC, then stuff results into dual-port ram. uC reads data via second ram port. Unless you need continuous sampling, then you must have a faster processor, most likely a DSP or graphics processor. If you can process the data completely off-line, then you can use simple ram, switched between uC and ADC controller.
If this is not for volume production, you might see if there is a USB oscilliscope module that will serve the need. That is probably an economical route if qty <=10-20 systems.
I agree - the STM32F429 can't handle 200 M samples/s.
You may find a DSP chip which will interface directly but based on the very little info you have provided I would go for an FPGA.
If you only need bursts of data the FPGA may not need any additional memory.
You need to tell us a lot more about the application (including how many you will need and if you are willing/able to design pcbs) to get good advice.
Just to add to things, and without knowing more about the application, you might also be able to use the FPGA to reduce the rate depending on what the samples look like. For example, for oversampling, you might be able to have a tracking and decimating subsystem in the FPGA. But it all depends on what you are trying to accomplish.
Can you tell us more about the app?
Just reading the data at speed, even in burst mode, doesn't do a lot of good if you cannot cook the raw data in time for the next burst.
Specifically, what is the data, and what are you going to do with it? eg is it a sine wave and you are going to do an FFT on it? Looking for an anomaly? Spike? variation in frequency or amplitude?
You may want to consider putting something in the FPGA to partialy cook the raw data (raw to rare) before passing it along. At a minimum, maybe keep some stats: variation in frequencey, max&min high/low, etc.
I have done this to capture acoustic echoes using a CPLD (Xilinx XC2C32)and a static RAM. The processor I used was the ATMega128 and I was able to tri-state the address/data bus from the Atmel and hand control over to the CPLD. This way I did not require dual port memory. Once the CPLD finished populating the data into RAM, the Atmel regained access to the SRAM to run cross-correlations on the captured data.