Ivan Cibrario Bertolotti (@Ivan Cibrario Bertolotti)
Cortex-M Exception Handling (Part 2)
The first part of this article described the conditions for an exception request to be accepted by a Cortex-M processor, mainly concerning the relationship of its priority with respect to the current execution priority. This part will describe instead what happens after an exception request is accepted and becomes active.
PROCESSOR OPERATION AND PRIVILEGE MODEBefore discussing in detail the sequence of actions that occurs within the processor after an exception request...
Cortex-M Exception Handling (Part 1)
This article describes how Cortex-M processors handle interrupts and, more generally, exceptions, a concept that plays a central role in the design and implementation of most embedded systems.
The short answer is yes, especially if you would like to build/certify a CAN-based product. I would recommend two things: 1) Check if your company or academic...
Please take this with a grain of salt because I'm not an expert on the Spartan. I did in on the Zynq though. You can use the DCM to generate a clock at the...
Hello,just my two cents: what about doing the opposite? Most function generators accept an external clock reference (often, at 10MHz). In my opinion it would...
Hello,to my opinion, one of the best references about protocol stack *implementation* in general (not specifically related to CAN) is still part IV of the book...
As a followup to the reply by maruthi.hr, let me describe the LPC2378 clock tree in some more detail (for what concerns the UART0 clock). Have a look at Fig....
Hello,I just had a quick look at your code, so take what I'm saying with a grain of salt. One thing I don't see is how you set the PCLKSEL0 register. It sets...
That's exactly my point... if FatFs works better or worse depending on whether or not you introduce manual delays it indicates that something is seriously wrong...
Hello,I concur with Tim about a possible timing issue. This is because, in a correctly integrated FatFs system (that is, with a hardware/RTOS adaptation layer...
If the stack frame is set up correctly, it should work because it would mimick exactly the normal exception exit sequence, except for the target PC.I did it myself...
It just came into my mind that a similar question (returning to an arbitrary thread-mode address from an ISR) was asked a couple of years ago for the Cortex-M3...
Hello,no problem, thanks for the extra information, it's hard to reason about these things without having a fairly complete picture. I have a couple of (hopefully...
Many operating systems do not support execution of unprivileged code (in this case thread-mode code) from within an interrupt handler at all. Microkernel-based...
Hello,as far as I know, the behavior you are observing is normal. There is an exception whose handling has not been completed, but the processor is currently executing...
I would just like to point out that the debate around event-driven programming has been going on for more than 20 years.It is an interesting approach for sure....
This is a very interesting observation, although I would not say it is a mixed metaphor. The C language, like most others, has been designed so that keywords...
In my opinion, there are two aspects worth considering in this question.The first one is about the basic mechanisms available at the language level to define variables...
Unfortunately, I am not an expert on the specific tool you are using. However, with similar tools, this kind of error is generally due to poor cabling and/or...
Hi Gill,the analogy between CAN error handling and interrupt handling escaped me at first, but it is indeed quite interesting. It highlights a nice analogy between...
In order to monitor bus health (and also their own health), CAN controllers must keep two counters, called transmit and receive error counter. They start at zero...
Hello everybody,just my tiny contribution to the discussion, on a side topic actually. Concerning the use of some areas of C++ (most notably exception handling...
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