Lightweight hardware abstraction
Hardware pin reassignments turned a small firmware tweak into a tangled mess of #ifdefs and scattered port references. Gene Breniman shows how a lightweight hardware abstraction, implemented with per-board include headers and meaningful macros like MODE_LED and LED_ON, cleans up the code and makes it easy to target multiple prototypes. The post emphasizes keeping changes local to configuration headers to reduce validation scope and maintenance.
A true pioneer passes away... A farewell to Ritchie.
Dennis Ritchie's work on C and UNIX quietly shaped the tools we use every day. Gene Breniman recalls becoming a convert after reading Kernighan and Ritchie's The C Programming Language and how C replaced assembly in his embedded projects. This personal farewell explains why K&R remains a near-biblical reference for many engineers and why Ritchie's influence still matters.
Deeply embedded design example - Logic replacement
Gene Breniman shows how a tiny PIC10F200 can replace a forest of discrete timing components to control six 10A H-bridges, letting firmware tune sequencing to cut EMI and reduce cost. He walks through analyzing the original RC/inverter delays, choosing the PIC, pinout and timer setup, and implementing compact assembly firmware that reproduces and improves the timing behavior. The result is fewer parts, saved board space, and better EMI control.
VHDL tutorial - A practical example - part 3 - VHDL testbench
Gene Breniman walks a complete VHDL testbench workflow for a CPLD-based data acquisition engine, from Xilinx ISE testbench generation to stimulus processes. He shows clock and SPI gating, a simulated ADC data generator tied to ADC_LRCK and ADC_BCK, and how simulation revealed a timing bug in the nvSRAM header that was then fixed in the VHDL. Practical and hands-on for verification work.
VHDL tutorial - A practical example - part 2 - VHDL coding
Gene Breniman walks through the VHDL coding for a CPLD-based data acquisition engine, turning the hardware spec into a working state machine and signal generators. The article explains SPI and I2S timing choices, an internal SPI peripheral latch, and counter-based timing (seqCount and CycleCnt) used to create LRCK, BCK, SPI SCK and nvSRAM write control. It’s a practical, implementation-focused guide for embedded designers.
VHDL tutorial - A practical example - part 1 - Hardware
Gene Breniman walks through a practical CPLD-based data acquisition engine built for a low-power handheld instrument, focusing on hardware choices, signal flow, and pin assignments. The article explains component selection including a PCM1870 ADC, CY14B101Q2 serial nvSRAM, and an XC2C64A CPLD, and shows how the CPLD acts as an SPI sequencer and I2S clock master while minimizing microcontroller pins and power draw.
Size matters - System success depends on initial design
A seemingly small UI choice can reshape an entire embedded system. Gene Breniman uses a real product example to show how picking a graphic touchscreen instead of a character LCD can multiply CPU, memory, OS, and licensing needs. The post explains why capturing requirements early and planning for growth paths keeps complexity and cost under control, and how to size hardware to fit real needs.
A part of history
At KVHS's 40th anniversary Gene Breniman reflects on how a tiny 100-milliwatt AM experiment grew into a high-power FM station and a launchpad for engineers. He credits teacher Ernie Wilson's hands-on mentorship for turning students into builders, and laments the loss of his high school's electronics program amid budget cuts. The post is a personal reminder why practical tech education and resourceful projects still matter.
I owe, I owe, so off to work I go.....
Gene recounts swapping startup plans for paid work to support family, taking an evening teaching role and then a full-time engineering job. He rediscovers the satisfaction of hands-on embedded design on an ARM9 system with FPGA/CPLD, learns which parts of entrepreneurship drained his time, and decides to keep his product work low-effort while finishing current projects. The post blends career lessons with practical engineering enthusiasm.
Software Prototyping
Software prototypes can save a lot of pain during bring-up, and Gene Breniman argues they deserve a place in the development process. He revisits an earlier post, then points readers to Jack G. Ganssle’s article on creating software prototypes, where test code becomes the model for the real product software. It is a short but practical reminder that early code can do more than just validate hardware.
VHDL tutorial
Gene Breniman presents a hands-on VHDL walkthrough for a programmable clock divider implemented on a Xilinx CoolRunner CPLD (XC2C32A). The example shows how to declare ports and internal signals, implement a clock-division process with reset and falling-edge detection, and create a simple addressable latch to select clock rates from a 40MHz master clock. It’s a compact, practical guide for embedded engineers learning VHDL and CPLD design.
VHDL tutorial - A practical example - part 3 - VHDL testbench
Gene Breniman walks a complete VHDL testbench workflow for a CPLD-based data acquisition engine, from Xilinx ISE testbench generation to stimulus processes. He shows clock and SPI gating, a simulated ADC data generator tied to ADC_LRCK and ADC_BCK, and how simulation revealed a timing bug in the nvSRAM header that was then fixed in the VHDL. Practical and hands-on for verification work.
VHDL tutorial - A practical example - part 1 - Hardware
Gene Breniman walks through a practical CPLD-based data acquisition engine built for a low-power handheld instrument, focusing on hardware choices, signal flow, and pin assignments. The article explains component selection including a PCM1870 ADC, CY14B101Q2 serial nvSRAM, and an XC2C64A CPLD, and shows how the CPLD acts as an SPI sequencer and I2S clock master while minimizing microcontroller pins and power draw.
VHDL tutorial - A practical example - part 2 - VHDL coding
Gene Breniman walks through the VHDL coding for a CPLD-based data acquisition engine, turning the hardware spec into a working state machine and signal generators. The article explains SPI and I2S timing choices, an internal SPI peripheral latch, and counter-based timing (seqCount and CycleCnt) used to create LRCK, BCK, SPI SCK and nvSRAM write control. It’s a practical, implementation-focused guide for embedded designers.
VHDL tutorial - Creating a hierarchical design
Complex VHDL files quickly become hard to read and maintain. This tutorial demonstrates how to break a design into reusable entities by building a divide-by-10 component, explaining ports, sensitivity lists, and the inout usage for a toggled output. It then shows how to instantiate and chain three instances into a ÷1000 divider, with synthesis notes from compiling to an XC2C128 device.
VHDL tutorial - part 2 - Testbench
In this follow-up Gene Breniman builds a VHDL testbench in Xilinx ISE, showing how to generate a continuous master clock, apply a power-on reset, and sequence register strobes to change clock divisors. He walks through timing waits and observation delays needed to verify ADC clock rates. The article also shows how simulation exposed a copy-paste bug in the original design.
VHDL tutorial - combining clocked and sequential logic
Need the ADC clock to sometimes be the raw 40MHz input? Gene Breniman shows how to extend a reloadable, counter-based VHDL clock divider to support a master-clock pass-through by using a conditional signal assignment to switch between the internal ADCClk and Mclk. The article also covers remapping ClkSel values and includes a working XC2C32A CPLD build that leaves room for future enhancements.
Deeply embedded design example - Logic replacement
Gene Breniman shows how a tiny PIC10F200 can replace a forest of discrete timing components to control six 10A H-bridges, letting firmware tune sequencing to cut EMI and reduce cost. He walks through analyzing the original RC/inverter delays, choosing the PIC, pinout and timer setup, and implementing compact assembly firmware that reproduces and improves the timing behavior. The result is fewer parts, saved board space, and better EMI control.
A true pioneer passes away... A farewell to Ritchie.
Dennis Ritchie's work on C and UNIX quietly shaped the tools we use every day. Gene Breniman recalls becoming a convert after reading Kernighan and Ritchie's The C Programming Language and how C replaced assembly in his embedded projects. This personal farewell explains why K&R remains a near-biblical reference for many engineers and why Ritchie's influence still matters.
Size matters - System success depends on initial design
A seemingly small UI choice can reshape an entire embedded system. Gene Breniman uses a real product example to show how picking a graphic touchscreen instead of a character LCD can multiply CPU, memory, OS, and licensing needs. The post explains why capturing requirements early and planning for growth paths keeps complexity and cost under control, and how to size hardware to fit real needs.
VHDL tutorial - A practical example - part 3 - VHDL testbench
Gene Breniman walks a complete VHDL testbench workflow for a CPLD-based data acquisition engine, from Xilinx ISE testbench generation to stimulus processes. He shows clock and SPI gating, a simulated ADC data generator tied to ADC_LRCK and ADC_BCK, and how simulation revealed a timing bug in the nvSRAM header that was then fixed in the VHDL. Practical and hands-on for verification work.
VHDL tutorial - part 2 - Testbench
In this follow-up Gene Breniman builds a VHDL testbench in Xilinx ISE, showing how to generate a continuous master clock, apply a power-on reset, and sequence register strobes to change clock divisors. He walks through timing waits and observation delays needed to verify ADC clock rates. The article also shows how simulation exposed a copy-paste bug in the original design.
VHDL tutorial
Gene Breniman presents a hands-on VHDL walkthrough for a programmable clock divider implemented on a Xilinx CoolRunner CPLD (XC2C32A). The example shows how to declare ports and internal signals, implement a clock-division process with reset and falling-edge detection, and create a simple addressable latch to select clock rates from a 40MHz master clock. It’s a compact, practical guide for embedded engineers learning VHDL and CPLD design.
VHDL tutorial - A practical example - part 2 - VHDL coding
Gene Breniman walks through the VHDL coding for a CPLD-based data acquisition engine, turning the hardware spec into a working state machine and signal generators. The article explains SPI and I2S timing choices, an internal SPI peripheral latch, and counter-based timing (seqCount and CycleCnt) used to create LRCK, BCK, SPI SCK and nvSRAM write control. It’s a practical, implementation-focused guide for embedded designers.
VHDL tutorial - Creating a hierarchical design
Complex VHDL files quickly become hard to read and maintain. This tutorial demonstrates how to break a design into reusable entities by building a divide-by-10 component, explaining ports, sensitivity lists, and the inout usage for a toggled output. It then shows how to instantiate and chain three instances into a ÷1000 divider, with synthesis notes from compiling to an XC2C128 device.
VHDL tutorial - A practical example - part 1 - Hardware
Gene Breniman walks through a practical CPLD-based data acquisition engine built for a low-power handheld instrument, focusing on hardware choices, signal flow, and pin assignments. The article explains component selection including a PCM1870 ADC, CY14B101Q2 serial nvSRAM, and an XC2C64A CPLD, and shows how the CPLD acts as an SPI sequencer and I2S clock master while minimizing microcontroller pins and power draw.
VHDL tutorial - combining clocked and sequential logic
Need the ADC clock to sometimes be the raw 40MHz input? Gene Breniman shows how to extend a reloadable, counter-based VHDL clock divider to support a master-clock pass-through by using a conditional signal assignment to switch between the internal ADCClk and Mclk. The article also covers remapping ClkSel values and includes a working XC2C32A CPLD build that leaves room for future enhancements.
Deeply embedded design example - Logic replacement
Gene Breniman shows how a tiny PIC10F200 can replace a forest of discrete timing components to control six 10A H-bridges, letting firmware tune sequencing to cut EMI and reduce cost. He walks through analyzing the original RC/inverter delays, choosing the PIC, pinout and timer setup, and implementing compact assembly firmware that reproduces and improves the timing behavior. The result is fewer parts, saved board space, and better EMI control.
Will work for tools!
Some engineers collect parts, Gene Breniman collects tools, and he makes a strong case for why they matter. In this personal piece, he traces that mindset back to his grandfather’s basement shop, where a love of building and problem-solving took root. From free FPGA tools to scopes, logic analyzers, and home-built test gear, the post is a reminder that the right tools can shape both a career and the products you ship.
Lightweight hardware abstraction
Hardware pin reassignments turned a small firmware tweak into a tangled mess of #ifdefs and scattered port references. Gene Breniman shows how a lightweight hardware abstraction, implemented with per-board include headers and meaningful macros like MODE_LED and LED_ON, cleans up the code and makes it easy to target multiple prototypes. The post emphasizes keeping changes local to configuration headers to reduce validation scope and maintenance.
