How to monitor the content of a memory address by software interrupt?

Started by charles_hans 5 years ago14 replieslatest reply 5 years ago446 views

I need to respond to the change of the content in a global variable or array, but do not want to poll it constantly. How to implement a software interrupt with ISR? I am not familiar with software interrupt. Please help. The platform could be Freescale 16-bit 9s12 or 32-bit MPC5744P. Thank you in advance.

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Reply by jeghartmanMarch 13, 2019

Hi Charles,

A JTAG or SWD debugger can normally be set up to give a breakpoint on data change if you want to do this for debugging.

If you want to do this in a running system, the only way I can think of is to use accessor functions on the data array. In other words, no software is allowed to update the array by direct access. All updates must call a function with the address and data to be updated. You write your accessor function to detect when specific addresses are updated and use that to trigger whatever you need.

If an interrupt is updating the array data. The accessor function can set a flag to be handled later.

Hope this helps.


Johan Hartman

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Reply by charles_hansMarch 13, 2019
Thank you all for your invaluable suggestions. My senario is as follows: This is a 3-core processor and an array is set up in a shared memory. What I need to do is to pass data between two cores. When one core writes on the array, I want the other core fetches the data immediately without pooling constantly (I know how to pool but think it clumsy). I have arranged a beacon to lock the array when writing/reading, avoiding racing.

I am not experienced in embedded programing. I have worked in high-level languages such as ASP.Net. When I build a text-box on a web-page, I can write code in the event-handler of the text-box. There is a ready-made event-handler "OnChange()" which is built in ASP.net. In my imagination I thought there should be a similar way to handle the same situation in the imbedded world. Please help. Thanks!

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Reply by VadimBMarch 13, 2019

> This is a 3-core processor and an array is set up in a shared memory.

Then, there should be a mailbox structure of some sort for inter-core communication, and especially mailbox interrupts. In case of MPC5744P you might consider SIPI (Serial Interprocessor Interface).

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Reply by mr_banditMarch 13, 2019
Sending a message with the data is the traditional way of doing this. More to the point:

1. are you only updating a byte or two, or is it a lot of data?

2. is this time critical - does the new data from process A to process B need to be handled within a specific period of time?

Generally, the reason for shared memory is sharing a large amount of data. It also has the associated issues of mutual exclusion, etc. Avoid it if you can.

If you are only dealing with some small amount of data (say, under 100 bytes or the general max size of a message, use a message.

If one of the reasons you need shared memory is keeping all data in sync, then you can send a message to the other process that says "I have new data".

You also did not say if you are using an RTOS or command loop. You imply you are using an RTOS, or some feature of the hardware (not familiar with this chip). It looks like we are assuming an RTOS.

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Reply by charles_hansMarch 13, 2019

Thank your for your advice. I have not decided to implement RTOS yet although my application is time-critical. Since I am not experienced in embedded programing, I thought there have been a well-known way known as "software interrupt" which I had been unaware of. If I need to build the communication between cores, I need to learn a lot of things before I could ask questions in this forum.

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Reply by mr_banditMarch 13, 2019

The most common (non-RTOS) is a "command loop":


loop( forever )




On shared memory/semaphores/etc: Modern micros offer HW support in the form if "test and set" opcodes. This is the only reliable method of securely doing exclusive access to shared memory via semaphores.

Now: you could have shared memory, but each MPU has write privileges - by convention - and multiple readers, but the readers would need to poll for new writes. You could setup a timer (as mentioned by SolderDot) which does the poll for you && read the new values and make a per-MPU copy. (I am assuming you are using a circular queue for the data.) 

In the stuff(): these are state-machines (finite automata) of some sort, or checks if something has changed, like received a message.

My question is, respectfully, if you are fairly new to embedded systems, why are you attempting something this complex? This is a 300/400 level university OS class sort of project, in addition to a fairly sophisticated embedded project. The embedded world is not an ASP.net environment - such environments hide a lot of things, where the embedded world basically is right on the iron.

What is the basic project?

You may want to look at an RTOS like uC/OS. A good way to get comfortable with uC/OS is get a board from netburner. Low-cost, solid, with coldfire micros && uC/OS out of the box. And full source. Not the current rev of uC/OS, but it has the basics.

You can then get a free demo full-source copy of the uC/OS (micrium.com). He only wants money if you try to make money. He has a good book on it. Well documented clean code.

Another choice is freertos  https://www.freertos.org/ This is another good way to learn the principles.

Quote: I need to learn a lot of things before I could ask questions in this forum

We don't mind helping. We do ask for folks to do their homework. We understand being stuck - all been there. And there are a lot of obscure things in this biz.

If your goal is to learn the embedded world, you have a lot of choices. My favorite vector is arduinos: cheap hardware, free toolchain, well documented AVR chips, with lots of demo code. Of course, there is a lot of poor code out there, but it seems you have the background to be able to tell the difference.

Success to you!

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Reply by charles_hansMarch 13, 2019
Thank you for your useful advices! I will explore the options once get time. 
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Reply by jmford94March 13, 2019

Post deleted by author

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Reply by Tim WescottMarch 13, 2019

This is not at all a normal thing to be doing.  What do you anticipate will be writing to the memory?

Usually if you have peripherals that DMA to memory, there is hardware in place to interrupt the processor when the transfer is complete.

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Reply by BVRameshMarch 13, 2019

A software interrupt is not useful for you purpose. If you are looking for change of content in an array, you can create a shadow array of same size and a timer interrupt compares both the main and shadow array. If there is a change in the shadow array you can trigger as that there is a change and copy the changed stuff to shadow array for future comparisons.

Hope this will solve your problem.

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Reply by KocsonyaMarch 13, 2019

Software interrupt is an interrupt triggered by software. That is, the ISR is started not because some hardware requests a service but because you execute a special instruction. 

It is pretty much like calling a subroutine (the ISR) except that the address of the subroutine is taken from the vector table and an exception stack frame is built instead of just pushing the return address. In addition, depending on the actual processor core, you get the interrupt disabled, the processor mode changed to supervisor mode etc. But, otherwise those details it's still just an expensive subroutine call.

So software interrupts won't help you to avoid polling.

As Tim Wescott asked, what do you want to do? 

What can change your global variable or array?

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Reply by SolderdotMarch 13, 2019

You could set-up a timer to periodically look into the variable and check for changes inside the timer ISR. But this should be done only to narrow down when, where and why the variable is written. Normally you would do that with other debug means, e.g. tracing, so you know what is going on inbetween the last two checks, i.e. the time window when the change took place.

So this may help you figure out by whom the memory content was changed, and then change the design of your software such that the desired action is triggered from that location, too.

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Reply by CustomSargeMarch 13, 2019

I'm with VadimB: if there isn't an inter-core comm, you'll have to make one. With separate chips I've used one pin to hit another that's set to interrupt - crude, but functional. It was for common ram just as yours.

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Reply by charles_hansMarch 13, 2019

Thank you all for your help. I got help from NxP support, which was indicated in the attached figure. Basically the software interrupt mode is the same for all NxP Bolero processors, therefore the implementation is device specific. The way is very similar to other standard interrupt. My e-mail address is charles_hans@yahoo.com. If you need further information please contact me.